Conference Paper

A low-cost concurrent error detection technique for processor control logic

DOI: 10.1145/1403375.1403592 Conference: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008
Source: DBLP


This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transient faults, the technique selects faults which have a high probability of causing damage to the architectural state of the processor and protects the circuit against these faults. Fault detection is achieved through a series of assertions. Each assertion is an implication from inputs to the outputs of a combinational circuit. Fault simulation experiments performed on control logic modules of an industrial processor suggest that high reduction in damage causing faults can be achieved with a low overhead.

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Available from: R. Galivanche, Jun 05, 2014
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    • "While transient errors that occur during circuit operation will require complex online error detection approach [4]–[6], permanent faults can be checked for during production and the chip can be discarded before it causes errors for the enduser . Circuit designers use variety of defect models to capture the behavior of a permanent defect in chip. "
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    • "Other researchers have considered relationships that occur between flip-flops or between circuit sites at the gate level. For example, the authors of [13] investigated the protection of the control logic of a microprocessor though the use of relationships between functions of the flip-flops in a design. The authors of [2] proposed the use of checking functions, which identify circuit sites or functions of circuit sites that should always be equal to (or complements of) each other. "
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