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Fully differential baseband pulse generator for IEEE 802.15.4a standard
Abstract
This paper presents a fully differential baseband pulse generator intended for Impulse-Radio Ultra-Wideband (IR-UWB) direct up-conversion transmitter architectures. The generator provides impulse related binary phase shift keying (BPSK) and on/off keying (OOK) modulation in accordance with the IEEE 802.15.4a standard. The logic part of the generator runs on a clock of 499.2 MHz allowing direct generation of single preamble impulses as well as data impulse bursts. While the pulse generator is digitally controlled at the input, the output provides an analogue signal ready to be shaped by a low-pass filter (LPF) and up-converted to the desired channel.
... It is achieved by utilising suitable pulse shaping techniques. One way is given in [7]. ...
Design, simulation, implementation and performance of IR-UWB baseband conforming to IEEE802.15.4a are discussed. The baseband can support various data rates such as 850 Kb/s, 6.81 Mb/s and 27.24 Mb/s. The design and parameter selection were considered carefully taking into account all possible imperfections that IR-UWB high frequency signal can experience. Energy detection receiver employing a comparator clocked at 499.2 MHz was adopted for the digitisation. Using I and Q path both positive and negative pulses were detected with a high reliability leading to a very good synchronisation performance. Simulation results confirm that the synchronisation is very robust being always correct for office NLOS environment and a large clock deviation between transmitter and receiver. The algorithm presented in this paper was implemented with discrete components, FPGA and signal generators. Experimental results show a good agreement with the simulation for all the data rates and the implemented baseband offers around six meter communication range tested along with a high frequency frontend from discrete components.
... With the aid of digital to analogue converter (DAC) three states are generated: positive and negative pulses and zeros indicating the need of 1.5 bits. Such a pulse generation scheme with differential signalling adopted for the HF frontend is considered in [8]. ...
One energy efficient way of ASIC implementation for the standard IEEE802.15.4a was considered in greater detail. The main focus was on developing a solution for short range communication based on impulse radio ultra wideband. The ASIC implementation is performed with the 250 nm SiGe technology from IHP, Germany. The current system consists of three chips: radio frequency frontend, digital baseband and an integrating analogue digital converter. All the chips were fabricated and designed at IHP. A non-coherent energy detection receiver was realised which collects energy over 16 ns in analogue fashion. The performance of the complete system was evaluated bringing the chips on a board. Our multiple ASIC approach was a necessary step towards a complete integration of the system into a single chip. This paper discusses the function of individual chips and their interaction on a board. The performance was assessed by frame error rates, approximate coverage and waveforms at certain points. Initial laboratory tests and measurements suggest that the implemented system can support wireless communications in a distance of up to five meters and consume reasonable power.
This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm2.
This paper presents a monolithically integrated ultra wideband direct up conversion transmitter designed in accordance with IEEE 802.15.4a standard. The transmitter operates in the higher UWB band in eight communication channels. It supports the burst position and the binary phase-shift keying modulation schemes and provides a modulated impulse sequence with a pulse repetition frequency up to 499.2 MHz. The transmitter is fabricated in a 0.25 μm BiCMOS technology and occupies a silicon area of 1.75×1.55 mm2.
This paper describes a monolithic integrated single-chip transceiver intended for Impulse Radio (IR) Ultra-wide Band (UWB) applications compliant with the IEEE 802.15.4a standard. The transmitter is designed to operate in the upper UWB band on the mandatory channel #9 (7.9872 GHz). In order to assure compliance with the standard, the transceiver components are designed towards higher degree of integration, low cost and low power consumption operation. The receiver employs a direct down-conversion concept. The transmitter is an implementation of the gated-oscillator-principle to generate short impulses of 2 ns duration. It provides OOK and BPSK modulation capability in accordance with the standard. A fully integrated frequency synthesizer delivers all necessary LO and clock signals for the receiver and the transmitter. In order to minimize the on-chip cross-talk all supply voltages are internally regulated. The circuit was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 2.25 × 2.35 mm2.
A fully integrated sub-psec jitter PLL realized in a standard digital 0.12µm CMOS copper technology with 1.5V supply is presented. A dual LC-VCO is implemented to support different standards for serial data transmission. We present the general concept and test chip results. Operating with a 311MHz reference clock the PLL achieves typ. 870fs integrated jitter, a phase noise of-115dBc/Hz @1MHz offset, on a 2.488GHz output with 45mW power and a module area of 0.7mm<sup>2</sup>.
In this paper, a novel fully integrated monocycle pulse based UWB transmitter is presented. Fabricated in a 0.18-mum CMOS process, a low-power all-digital UWB pulse generator and modulator is proposed. The modulated pulse is further shaped by a driver amplifier. The transmitted pulses are binary phase modulated and meet the FCC UWB low frequency band (3.1-4.5GHz) spectral mask specification
This paper describes a monolithic integrated transmitter intended for impulse radio (IR) Ultra-wide band (UWB) applications including indoor communication and indoor localization. The transmitter operates in the higher UWB band centered at 7.68 GHz and it is optimized for a pulse bandwidth of about 1.5 GHz. The transmitter generates single pulses with a repetition rate of 60 MHz and utilizes pulse position modulation (8-PPM) for data communication. A dedicated time-of-arrival (TOA) measurement extension supports precise indoor localization in conjunction with an appropriate UWB receiver. The demonstrated spatial ranging resolution is about 3.9 centimeter under line-of-sight conditions.
The work presented in this paper is the first integrated design that conciliates full digital reception, emission and baseband with low power consumption in the 4-to-5 GHz band. Power consumption is an important issue of digital reception when digitization of the RF signals into N bits needs frequencies up to 20 GHz. We hereafter describe a non-coherent receiver that simply digitizes the signal asynchronously on only one bit and calculates the signal power in a 500 MHz bandwidth. The sampling frequency is hence reduced to 1 GHz while the 1b conversion simplifies the design and consequently reduces the power consumption. The proposed transmitter also has mostly-digital architecture. It achieves low power consumption by generating pulses without use of high frequency synthesis and by activating the generator only during pulse emission. Low power consumption and integration level are further improved by using an integrated digital baseband that can be optionally activated.
The paper describes an ultra-wideband transmitter, which incorporates an innovative carrier-based pseudo-Gaussian pulse generator satisfying FCC rules with no-filter and high spectral efficiency. The design includes a BPSK modulator, a ramp generator and an output buffer. The transmitter is designed for run up to 500 Mpps in the UWB 3-5-GHz band and it is implemented in 0.28-mum CMOS technology with a core chip size of 0.06-mm<sup>2</sup>. It allows the use in various UWB applications. Pulse generator dissipation is 1.9-mW.
A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.
This paper presents calculations for approximating the measured spectrum of pulsed signals in the high and low pulse-repetition-frequency (PRF) region. Experimentally verified peak and average power calculations are presented for pulse trains with no modulation and when modulated by random data using binary phase-shift keying (BPSK). A pulse generator is presented that is built using commercially available discrete components. BPSK pulses are generated at a PRF of 50 MHz. The output spectrum has a center frequency of 5.355 GHz and a -10-dB bandwidth of 550 MHz. A technique for pulse shaping is presented that approximates a Gaussian pulse by exploiting the exponential behavior of a bipolar junction transistor. This technique is demonstrated by a pulse generator fabricated in a 0.18-μm SiGe BiCMOS process. BPSK pulses are generated by inverting a local oscillator signal as opposed to the reference pulse, improving matching. Pulses are transmitted at a PRF of 100 MHz and centered in 528-MHz-wide channels equally spaced within the 3.1-10.6-GHz ultra-wideband band. Measurement results for both transmitters match well with calculated values.
This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm<sup>2</sup> using 0.6-μm digital CMOS technology
A fully integrated sub-psec jitter PLL realized in a standard digital O. 121m CMOS copper technology with 1.5V supply is presented. A dual LC-VCO is implemented to support different standards for serial data transmission. We present the general concept and test chip results. Operating with a 311MHz reference clock the PLL achieves typ. 870J integrated jitter, a phase noise of-115dBc/Hz IMHz of Jet, on a 2.488GHz output with 45mW power and a module area of O. 7mm .
A 0.18í µí¼m CMOS802.15.4a UWB transceiver for communication and localization
- Y Zheng
- M Annamalai
- K Arasu
- Y Wong
- The
Y. Zheng, M. Annamalai Arasu, K. Wong, Y. The et al., " A 0.18í µí¼m CMOS802.15.4a UWB transceiver for communication and localization ", ISSCC Dig. Tech. Papers 3-7 Feb. 2008, On page(s): 118-600.
Gaussian pulse generator for subbanded ulta-wideband transmitter
- D Wentzloff
- A Chandrakasan