A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels

Conference Paper · December 2006with31 Reads
DOI: 10.1109/APCCAS.2006.342541 · Source: DBLP
Conference: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006


    Design of a fully pipelined multiplierless digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial results of the convolution sum. The new architecture performs computations in log-domain by utilizing low complexity log2 and inverse-log2 approximation modules. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of the multipliers in the architecture. The proposed architecture is capable of performing convolution operations for 181.3 1024 times 1024 frames or 190.1 million outputs per second with 22 times 22 kernels in a Xilinx's Virtex XC2V2000-4ff896 FPGA at maximum clock frequency of 190.1 MHz. The throughput of the new design is 3.17 times higher when compared with that of the previous implementations (Zhang et al., 2005). Evaluation in Xilinx's core generator showed that the proposed design results in 60% reduction in hardware resource when compared to the design using pipelined multipliers