This paper studies the di-culty of predicting interconnect delay in an industrial setting. Fifty industrial circuits, Al- tera's Quartus II CAD software, and Altera's Stratix and Stratix II FPGA architectures were used in the study. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high de- gree of accuracy. Futhermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Finally, we examine the beneflts of using the simple timing model in a timing driven physical synthesis ∞ow, and attempt to establish an upper bound on these possible gains, given the di-culty of interconnect delay prediction. of interconnect delay even before the physical design steps (placement and routing) in an FPGA CAD ∞ow are exe- cuted is a di-cult yet important problem. The ability to predict interconnect delay early in the CAD ∞ow ofiers two advantages. First, the timing driven restructuring opera- tions carried out during the early CAD steps (synthesis and technology mapping) can be made much more efiective if in- terconnect delay can be predicted with reasonable accuracy. Second, the delay predictions can be used to provide feed-