IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010 185
Double Patterning Layout Decomposition for
Simultaneous Conflict and Stitch Minimization
Kun Yuan, Jae-Seok Yang, and David Z. Pan, Senior Member, IEEE
Abstract—Double patterning lithography (DPL) is considered
as a most likely solution for 32nm/22nm technology. In DPL,
the layout patterns are decomposed into two masks (colors),
and manufactured through two exposures and etch steps. If
the spacing between two features (polygons) is less than certain
minimum coloring distance, they have to be assigned opposite
colors. However, a proper coloring is not always feasible because
two neighboring patterns within the minimum distance may be
in the same mask due to complex pattern configurations. In that
case, a feature may need to be split into two parts to resolve the
conflict, resulting in stitch insertion which causes yield loss due to
overlay and line-end effect. While previous layout decomposition
approaches perform coloring and splitting separately, in this
paper, we propose a simultaneous conflict and stitch minimization
algorithm with an integer linear programming (ILP) formulation.
Since ILP is in class NP-hard, the algorithm includes three
speed-up techniques: 1) grid merging; 2) independent component
computation; and 3) layout partition. In addition, our algorithm
can be extended to handle design rules such as overlap margin
and minimum width for practical use as well as off-grid layout.
Our approach can reduce 33% of stitches and remove conflicts
by 87.6% compared with two phase greedy decomposition.
Index Terms—Double patterning lithography, integer linear
programming, layout decomposition.
due to the delay of the next generation lithography equipment
such as extreme ultraviolet . Double patterning lithogra-
phy (DPL) – emerges almost the only alternative for
32nm/22nm nodes and it is already used for NAND-flash
production. In DPL, a single layout is decomposed into two
masks and manufactured through two exposure/etching steps.
As a benefit, the pitch size is doubled, which enhances the
resolution as illustrated in Fig. 1. Although DPL requires two
masks and increases the design cost, it is widely considered
as a most likely solution for 32nm, 22nm, and even 16nm.
Double patterning layout decomposition – is a process
that assigns two features within the given minimum space
S the minimum feature size decreases, semiconductor
industry is facing the limitation of patterning sub-32nm
Manuscript received June 9, 2009; revised August 17, 2009. Current version
published January 22, 2010. This paper was supported in part by the National
Science Foundation, Semiconductor Research Corporation, Sun, Qualcomm,
and equipment donations from Intel. This paper was recommended by
Associate Editor P. Saxena.
The authors are with the Department of Electrical and Computer
Engineering, University of Texas, Austin, TX 78731 USA (e-mail:
firstname.lastname@example.org; email@example.com; firstname.lastname@example.org).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2009.2035577
is increased effectively in DPL.
One single design is decomposed into two masks and the pitch size
to different masks. A layout may contain a pattern which
is unable to assign a color. In this case, a feature may be
split into two parts and colored differently to resolve the
conflict, which generates stitches. Stitches will cause yield
loss and increase manufacturing cost due to overlay errors,
which is 5nm or 6nm under current 32nm double patterning
lithography. Some mask misalignment direction  could be
actually beneficial for printability. However, on the presence of
various process uncertainties, such as dose, focus, and mask
errors, the printed stitch width could be easily smaller than
25nm and result in design failure. Pushing overlay below
3nm  is very challenging. Moreover, the additional line-
ends may cause more pattern degradation and reduce yield
in case of defocus and dose variation. After splitting, a few
unresolved or even unresolvable conflicts may remain and will
be corrected by time consuming layout redesign. Therefore, it
is important to produce high quality decomposition solution
with less conflicts and stitches.
There are a few works focusing on stand-alone layout
decomposition. A heuristic approach is proposed in  to
cut troublesome patterns after finding the coloring conflicts.
The patterns are prefragmented into smaller pieces in  to
perform coloring. All these works do not have a systematical
way to minimize the number of conflicts and stitches. Coloring
and splitting are considered in separate steps while they are
highly correlated tasks. Pattern matching technique is proposed
in  to decompose the layout. However, it might not be
able to work on large scale problem, hence limits the solution
quality. Recently, a practical layout decomposition flow is
proposed in  to address design needs for double patterning.
They first detect the features associated with unresolvable
conflict cycles for layout modification. The remaining design
is then decomposed to minimize the number of stitches based
on an ILP formulation. However, in their work, the number
of unresolvable conflict cycles and splitting stitches are not
optimized together, and conflict elimination technique is quite
0278-0070/$26.00 c ? 2010 IEEE
186IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
Fig. 2.Concept of conflict and stitch.
In this paper, we propose an algorithm to decompose layout
for minimizing conflicts and stitches simultaneously. The
proposed approach reduces the conflicts by 87.6% with 33%
less stitches compared to a greedy two phase decomposition
flow. When compared to a methodology based on , we are
also able to achieve averagely 87.2% and 10% reduction on
conflicts and stitches, respectively. Although our approach is
comparatively slower, we can obtain coloring solutions for all
the test cases within a few minutes. The runtime shows linear
complexity with respect to problem size.
Our main contributions are as follows.
1) We propose a new grid model to enable bigger solution
space than previous works ,  and perform simul-
taneous conflict and stitch optimization.
2) We develop an ILP algorithm to minimize the number
of conflicts and stitches for a high quality solution.
3) We propose three speed-up techniques (grid merging,
independent component computing and layout partition)
to improve the runtime and scalability of our algorithm.
For layout partition, we identify and solve a coloring
flip optimization problem to minimize the conflicts and
stitches across the boundary of different partitions.
4) We discuss how to extend our proposed grid model
to handle various splitting rules and design patterns in
The rest of the paper is organized as follows. Section II
provides the preliminaries and motivates. In Section III, we
discuss the problem formulation with related model and defi-
nitions. The basic ILP formulation is described in Section IV
with three speed-up techniques. The extensive discussion
on grid model for practical design issues is presented in
Section V. Section VI presents the experiment results and
Section VII concludes this paper.
II. Preliminaries and Motivation
A. Double Patterning Layout Decomposition Considerations
As explained in Section I, in DPL, the original design will
be assigned into two masks. There are two critical issues with
this layout decomposition: coloring conflict and splitting stitch.
1) Coloring Conflict: If the distance between two separate
features is less than minimum coloring spacing mincs, they
works , . An unplanned coloring will need much extra effort during
Shortcoming of two phase layout decomposition flow in previous
should be assigned to different masks (colors). Otherwise,
there will be a coloring conflict.
Fig. 2(a) shows a layout with three features, and any two
of them are required to have different colors because of the
insufficient spacing. A coloring conflict will be unavoidable
as in Fig. 2(b). Sometimes, such a violation can be eliminated
by appropriately splitting the features like Fig. 2(c). There
are also unresolvable conflicts, as Fig. 2(d) indicates, which
requires modifying the design.
Splitting Stitch: The stitch exists when two touched
features are assigned to different masks. The stitch can be
inserted to split some features to resolve the conflict as shown
in Fig. 2(c). However, stitch insertion can have negative effects
on yield due to overlay error between the two masks as
Fig. 2(e) illustrates. In addition, the line-end will cause pattern
There are several practical guidelines for splitting. As
Fig. 2(f) shows, in order to control the overlay, there is a
minimum overlap length, minol, requirement for stitch inser-
tion. The segments h1 and h2 on different masks should be
overlapped to certain amount ensuring better manufacturabil-
ity. Moreover, we do not want to have any minimum width,
minwi, rule violation during splitting, as marked by the circle
in Fig. 2(f).
Without altering layout in the scope, the general objective
of layout decomposition can be stated as minimizing the
unresolved conflicts by introducing as few as possible stitches.
B. Simultaneous Optimization
The previous works insert stitches after coloring to resolve
conflicts. Without planning possible splitting during coloring,
it is hard to eliminate the conflict. Considering a layout in
Fig. 3(a), we have a coloring solution in Fig. 3(b). During
the splitting, the U feature should be cut into two parts to
remove the conflict but we have to further check whether
the splitting will result in another conflict like Fig. 3(c). In
such case, the coloring of the neighborhood features needs to
be reconsidered to avoid unnecessary stitches like Fig. 3(d)
and enable optimal solution in Fig. 3(e) or (f). This is a
simple example, but as we can see, given the complexity
of modern design, the two-phase approach will have extreme
difficulty handling the exploding consideration and producing
YUAN ET AL.: DOUBLE PATTERNING LAYOUT DECOMPOSITION FOR SIMULTANEOUS CONFLICT AND STITCH MINIMIZATION 195
C. Coloring Flip Optimization
Table VII shows the improvement when coloring flip is
applied to merge solutions. This optimization will only be
applied to relatively bigger independent components, which
require proposed layout partition technique to further reduce
problem size. Therefore, in Table VII, we only list the statistics
for these bigger components in the respective benchmarks. The
conflict and stitch number from smaller components without
layout partitioning applied are not included.
In Table VII, “CGPlp” and “SGPlp” denote the total number
of CGPs and SGPs for the independent components which
adopt layout partition. The percentage of this type of com-
ponents is very small, as shown in Table V. However, their
conflict and stitch number have relatively much bigger portion
when compared to the respective data under column “our
algorithm” in Table IV.
external conflict and stitch grid pairs. The results show that
there are outstanding “CGPe
mization. “with coloring flip” can reduce CGPe
70% and 40%, about 25% and 8% for total CGPs and SGPs.
This experiment demonstrates the necessity of coloring flip
optimization and the effectiveness of our ILP-based approach.
The CPU time difference between “without coloring flip” and
“with coloring flip” is very tiny and not listed.
lp” and “SGPe
lp” are the number of corresponding
lp” and “SGPe
lp” for further opti-
In this paper, we have developed a double patterning aware
layout decomposition flow for simultaneous conflict and stitch
minimization. Experimental results are very promising. In
future, we would like to study earlier stage placement/routing,
and standard cell designs to produce DPL-friendly layout.
The authors would like to thank Dr. M. Cho at IBM
Research for his helpful discussions on this problem.
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Kun Yuan received the B.S. degree in electronic
engineering and information science from the Uni-
versity of Science and Technology of China, Hefei,
China, in 2004. He is currently working toward the
Ph.D. degree in electrical and computer engineering
at the University of Texas, Austin.
He was with TeraRoute, Austin, TX, during the
summer of 2007 as a software engineering intern,
and with NVIDIA, Santa Clara, CA, during the
summer of 2009 as a hardware engineering intern.
His current research interests include physical design
automation for manufacturability and numerical optimization.
Mr. Yuan received the Microelectronic and Computer Development Fellow-
ship for 2006–2008, the International Symposium on Physical Design Routing
Contest Award in 2007, and the Best Paper Award Nomination at the Asian
and South Pacific Design Automation Conference in 2010.
Jae-Seok Yang received the B.S. degree in electrical
engineering from Sogang University, Seoul, Korea,
in 1997, and the M.S. degree in electrical engineer-
ing and computer science from the University of Cal-
ifornia, Berkeley, in 2007. He is currently working
toward the Ph.D. degree in electrical and computer
engineering at the University of Texas, Austin.
From 1999 to 2005, he was with Samsung Semi-
conductor Research Center, Hwasung, Korea. His
research interests include nanometer very large scale
integration design for manufacturability and design
automation for 3-D integrated circuit design.
Mr. Yang was the recipient of the Best Paper Award at the System-on-a-
Chip Design Conference, Seoul, Korea, in 2002, the Samsung Scholarship in
2005, and the Best Paper Award Nomination at the Asian and South Pacific
Design Automation Conference in 2010.
David Z. Pan (S’97–M’00–SM’06) received the
Ph.D. degree in computer science from the Univer-
sity of California, Los Angeles, in 2000.
From 2000 to 2003, he was a Research Staff
Member with the IBM T. J. Watson Research Center,
Yorktown Heights, NY. He is currently an Associate
Professor and the Director with the UT Design
Automation Laboratory, Department of Electrical
and Computer Engineering, University of Texas,
Austin. He has published over 100 refereed papers
in international conferences and journals, and is the
holder of six U.S. patents. His research interests include nanometer very large
scale integration (VLSI) physical design, design for manufacturing, low-power
vertical integration design and technology, and design/computer aided design
(CAD) for emerging technologies.
Dr. Pan has served as an Associate Editor for the IEEE Transactions on
the IEEE Transactions on VLSI Systems, the IEEE Transactions on
196IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
Circuits and Systems-Part I, the IEEE Transactions on Circuits
and Systems-Part II, and the IEEE Circuits and Systems Society
Newsletter. He was also a Guest Editor of the TCAD Special Section on
“International Symposium on Physical Design (ISPD)” in 2007 and 2008. He
serves as the Chair of the IEEE Comuter Aided Network Design Committee
and the Association for the Computing Machinery (ACM)/Special Interest
Group on Design Automation (SIGDA) Physical Design Technical Commit-
tee. He is in the Design Technology Working Group of the International
Technology Roadmap for Semiconductor. He has served in the Technical
Program Committees of major VLSI/CAD conferences, including the Asia and
South Pacific Design Automation Conference (ASPDAC) (Topic Chair), the
Design Automation Conference, the Design, Automation and Test in Europe,
the International Conference on Computer Aided Design (ICCAD), the ISPD
(Program Chair), the International Symposium on Quality Electronic Design
(Topic Chair), the International Symposium on Circuits and Systems (CAD
Track Chair), the Proceedings of the System-Level Interconnect Prediction
(Publication Chair), the Great Lakes Symposium on VLSI, the Austic Con-
ference on Integrated Systems and Circuits (Program Co-Chair), International
Conference on Integrated Circuit Design and Technology, and the VLSI-
Design, Automation, and Test (EDA Track Chair). He is the General Chair
of the ISPD 2008 and the Steering Committee Chair of the ISPD 2009. He
is a Member of the Technical Advisory Board of Pyxis Technology, Inc.
Dr. Pan has received a number of awards for his research contributions and
professional services, including the ACM/SIGDA Outstanding New Faculty
Award in 2005, the National Science Foundation CAREER Award in 2007,
the Semiconductor Research Corporation Inventor Recognition Award thrice
in 2004, 2005 and 2006, the IBM Faculty Award thrice from 2004 to
2006, the UCLA Engineering Distinguished Young Alumnus Award in 2009,
the IBM Research Bravo Award in 2003, the SRC Techcon Best Paper
in Session Award in 1998 and 2007, the Best Student Paper Award from
the 2009 IEEE International Conference on Integrated Circuit Design and
Technology, the Dimitris Chorafas Foundation Research Award in 2000, the
ISPD Routing Contest Awards in 2007, the eASIC Placement Contest Grand
Prize in 2009, five Best Paper Award Nominations at the Design Automation
Conference/ICCAD/ASPDAC, and the ACM Recognition of Service Award
in 2007 and 2008. He was a Cadence Distinguished Speaker in 2007 and an
IEEE Circuits and Systems Society Distinguished Lecturer during 2008–2009.