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Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS
Abstract
Linearity and intrinsic gain enhancement tech- niques for realizing high-performance and low-voltage analog circuits in a deep-submicron CMOS are introduced. In place of a differential amplifier for the voltage-to-current (V/I) conversion at the input, a V/I conversion using a linear resistor and a positive feedback in a pseudo-differential configuration was adopted. The positive feedback concept was also applied to enhance the intrinsic gain of the deep-submicron MOS transistor which is used as a current source to realize high output impedance in amplifiers. In order to verify the effectiveness of the proposed techniques, a MOS 7th-order Gm-C linear phase low-pass-filter (LPF) was realized using a 65-nm CMOS process. Evaluation results showed that the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, less than -55 dB with a 100-MHz input and +10.3 dBm, respectively, all with a §0.1 Vp-p signal input at each input terminal in pseudo differential configuration, while the LPF including an output buffer dissipated 60 mW from a 1.2-V supply.
This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm
2
and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/√Hz, and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65 nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, ≤ -55 dB with a 100 MHz input, and +10.3 dBm, respectively, all with a ±0.1 Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60 mW in the case of a 1.2 V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.
An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-nVradicHz input-referred noise density, a -8-dBV out-of-band third-order intermodulation intercept point, and a +15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.
A full CMOS seventh-order linear phase filter based on gm-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-μm CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mVpp. The filter active area is only 900 × 200 μm2. The supply voltages used are ±1.5 V.
This paper introduces a high-speed and high-accuracy current-mode sample-and-hold (S/H) circuit that adopts the new linearization technique to the resistor-based voltage-to-current converted input current. The pseudo differential configuration is used to form the whole S/H circuit in order to cancel the clock feedthrough from the S/H switch. The circuit is designed and fabricated by using the 0.35 mum CMOS process. The power supplies are 2 V for the analog part and 2.5 V for the logic part. The 1.34 MHz input signal with a -5 dB of full-scale current was applied to the S/H IC, and the measured distortion was -68 dB. The S/H IC operated with a signal-to-noise ratio (S/N) of 57 dB up to 10 MHz input signal when the clock frequency was 20 MHz, and with a S/N of 50 dB at 17.5 MHz input signal when the clock frequency was 35 MHz
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. An OTA design with the proposed broadband linearization method has third-order inter-modulation (IM3) distortion better than -74 dB up to 350 MHz with 0.2V¿¿ input, 70 dB signal-to-noise ratio (SNR) in 1 MHz bandwidth, and 5.2 mW power consumption. The distortion-cancellation technique enables an IM3 improvement of up to 22 dB compared to a commensurate OTA without linearization. A proof-of-concept low-pass filter with the linearized OTAs has a measured IM3 < - 70 dB and 54.5 dB dynamic range over its 195 MHz bandwidth. The standalone OTAs and the filter were fabricated on a 0.13 ¿m CMOS test chip with 1.2 V supply.
A continuous-time fourth-order equiripple linear phase filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feed- back circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transcon- ductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter 3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The 43 dB of IM3 at filter cutoff frequency is obtained with 4 dbm two-tone signals. Implemented in 0.18- m CMOS process, the chip occupies 1 mm and consumes 175 mW at a 1.5-V supply voltage.
A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.
The recent explosion in the demand for mobile telecommunication, computing and multimedia applications has resulted in much interest in system on chip (SOC) applications. In this work, an analysis of the analog characteristics of scaled MOSFETs is presented. An analog performance metric of intrinsic gain, fT, linearity, and gm/Ids ratio is considered. The effect of scaling on various trade-offs is presented It has been shown that while scaling gate length (Lg) improves various trade-offs, scaling oxide thickness (Tox) and source/drain extension junction depth (Xj) do not impact trade-offs significantly and they can be set by other constraints such as power supply and gate leakage currents.
A novel pulse equalizer for hard disk systems is discussed.
Opposed to classical realizations, it is full CMOS while operating at 50
MHz cutoff frequency. It is explained how the equalizer can be extended
with a selective boost of 13 dB around the cutoff frequency for pulse
slimming. The equalizer is a gm-C seventh-order, 0.05°
equiripple-on-the-phase low-pass filter. It is made out of biquads with
matched integrating nodes. The inaccuracies are compensated with a novel
tuning system. This guarantees a ripple on the group delay of 2%. The
results are confirmed on 0.7-μm CMOS silicon