HOOVER: Hardware Object-Oriented Verification
Mostafa M. Aref Khaled M. Elleithy
Information And Computer Science Dept. Computer Engineering Department
King Fahd University of Petroleum and Minerals
Dhahran 3 1261, Saudi Arabia
In this paper a new formal hardware verification
approach based on
object oriented techniques is
presented. The HOOVER sysrem (Hardware Object
Orienfed VERification) is described. A cell library of
different hardware componenrs has been implemented as
classes. Components in the cell library are described at
the transistor level, gate level, and logical level, and
functional level. The verrficafion of a CMOS inverter and
I-bit CMOS adder using HOOVER is given in the paper.
The design process is a transformation between different
specifications (Figure I). An input algorithm may be
a specific algorithmic specification
language. Architecture may be specified using a
realization specification language. The role of design can
be viewed as a transformation process between the
algorithm specification language and the realization
specification language. The objective of any design
procedure is to produce an architecture that correctly
implements the required behavior subject to a given set of
constraints on area and timing. It is very expensive to
fabricate a design before verifying the functional
correctness of the design. There are hvo approaches for
and formal veritication.
Simulation is efficient for small size architectures where it
is possible to exhaustively run the simulator. Formal
verification is suitable for large size architectures.
A verification methodology is formal if it satisfies the
following characteristics [l]:
There is a formal framework to describe the
There is a formal technique to prove that
implementation and specifications are equivalent
without physically construct or simulate the design.
It is possible to manipulate and study the design’s
performance without the physical implementation.
Figure 1: A Hierarchical Representation of Design and
The heart of any formal verification methodology,
then, is the availability of a formal specification language
where formal proofs can be driven. Logic is one of the
most widely used specification languages for verification.
First order logic has been used in a number of systems [2-
41. Higher order logic has been used in a number of
applications [S-S]. Joyce [7-S] used HOL system to verify
a microprocessor. Temporal logic is an appropriate
approach for specifying timing characteristics of a design.
Temporal logic has been successfully used for verification
in [9-IO]. Productions systems have been used in formal
verification [I I].
Object Oriented Paradigm (OOP) have been proven
successful in software engineering due to its reusability
which increases design productivity. Object oriented
techniques provide a number of features, discussed in
section 2, which fit hardware verification. In [l2], Nebel
argued the suitability of object oriented techniques in
hardware system design. Several proposals where
adopt OOP in hardware description
languages such as VHDL [l3-151. In [l6], Schumacher
discussed the problems in these approaches.
In this paper we are introducing a novel approach for
hardware verification based on OOP. The HOOVER
(Hardware Object Oriented VERitication) system is
introduced. In section two an overview to object oriented
techniques is given. In section 3 the HOOVER system is
discuused. Examples using the HOOVER for verification
are given in
section 4. Finally, section 5 offers
conclusions and future extensions.
2. Object Oriented Techniques
The characteristics of an object-oriented language are:
abstraction: is a higher level, more intuitive
representation for a complex concept;
encapsulation: is the process whereby the
implementation details of an object are masked by
a well-defined external interface;
inheritance: where classes may he described in
terms of other classes by use of inheritance;
polymorphism: is the ability of different objects
to respond to the same message in a specialized
dynamic binding: is the ability to defer the
selection of which specific message-handlers will
be called for a message until run-time.
In HOOVER, a Cell Class Library is build based on
of hardware components. These
components are organized in a hierarchy that allows
inheritance of common attributes hehwen different
components. The behavior description is the only
attribute of these components (i.e.
encapsulation). The hierarchy structure of the Cell Class
Library allows the component of common attributes to be
on the top level (i.e. abstraction). Dealing with these
components description would be only through messages.
The same message may he passed to two different
components that results two different responses (i.e.
3. HOOVER System
HOOVER is a hardware object oriented verification
system. The circuit structural and behavioral descriptions
are HOOVER inputs. The circuit description would be
one or a combination of different hardware descriptions.
These descriptions include transistors, gates, logical,
functional, and module descriptions. HOOVER has a class
hierarchy contains Cell Class Library. The Cell Class
Library contains a predetined set of hardware
components. It consists of five subclass libraries represent
the five level of hardware descriptions. These subclass
libraries are Transistor-level Class Library (TCL), Gate-
level Class Library (CCL), Logic-level Class Library
(LCL), Function-level Class Library (FCL), Module-
level Class Library (MCL). The block diagram of
HOOVER is shown in Figure 2
Figure 2: The Block Diagram of HOOVER
Each cell class contains several properties describe its
inputs, outputs and behavior. The behavior ofthe cells is
described through methods that may be inherited to (or
override by) the subcells. Some examples of these classes
are shown below.
Examples of Classes
inputs: i outputs: 0
inputs: b, s
diagram: , s
send d depends on tbe logical level of the
base h and s
An n-type transistor is an instance of the transistor class.
The method is overridden by:
send d = s if logical level of the base b is 0
An p-type transistor is an instance of the transistor class.
The method is overridden by:
send d = s if logical level of the base b is I
inputs: il,i2, . . . i.
methods: 0r(i,,i2, i.,o)
inputs: i&, i.
methods: And(i&, i.,o)
send o = i, A iz A . . . A i.
The cell class library is a hierarchy structure. The top
class represents a simple hardware component; connection
class. In the same cell library, there exist different
transistor level components. As we move down the
specific hardware components are
described. These components may inherit some
characteristic from the upper ones.
Several circuit examples are used as input to
These examples include transistor/gate circuit
(e.g. invert@, transistor/logic circuit (e.g. l-bit full adder)
and logic/function circuit (n-bit full adder). Here, two
examples are presented. The first one is a CMOS inverter.
The second one is a l-bit full adder.
Exam& I :
A CMOS inverter consists of power, ground, p-transistor
and n-transistor components as shown in Figure 3.
Figure 3: A CMOS lnverter
The circuit description of the inverter is described as a
set of instances from the exiting classes as follows.
The behavioral description of the inverter is as follows
output = invert(input)
For i = 0, HOOVER sends 0 to Connection, and
Connection,. Their methods Comm(i,b,) and Comm(i,b*)
send b, and b2 equal 0 to Ntransistor, and Ptransistor,.
The method ofNhansistor,, NTrans(b,,p,,o), sends o = p,.
That means the output equals 1.
Similarly, for i = 1, HOOVER sends I to Connection,
and Connection2. Their methods Comm(i,b,) and
Comm(i,b2) send b, and bz equal 1 toNtransistor, and
Ptransistor,. The method of Ptransistor,, PTrans(b2,p2,0).
send o = pz. That means the output equals O.This show
that the circuit description verities the behavioral
A l-bit CMOS full adder consists of oower. eround.
12 p-type transistors and 12 n-type transistdrs, as shown ii
Figure 4: A l-bit CMOS Full Adder
The circuit description of the adder circuit is as follows.
For a = 0. b = 0, ck = 0
The following classes receive inputs:
The behavioral description of the adder circuit is given in
a logical level as follows.
sum = aOb@c;?i
Ntransistor,,(b,pB,pII) and Ntransistor,,(a,plo,p,,)
They send the following:
Ps = PO, Pb = PII3 PI = Ps, Ph = Ps, Pi = PIi13
which means that p& = 0, p, = 0, pu = 0. Then the class
Ntransistor3(p,,c,,,,p,,) send c,,, = p,, which means c,“~
equals 0. The final HOOVER’s output indicates that the
behavioral description is equivalent to the circuit
The verification of large-scale systems is no more a
straightforward process that can be completely achieved
using traditional approaches of simulation. In this paper
we aie describing a novel formal verification approach
based on object-oriented paradigm. A cell class library
that supports the HOOVER has been analyzed at different
specification levels. Examples of the transistor, gate,
logical, functional cell class libraries have been
implemented in HOOVER 1.0 using Java. To illustrate the
idea, a number of small size examples have been
presented in this paper.
Currently, we are working to complete the cell class
library in HOOVER to be able to test complex examples.
A module level class library will be implemented. The
new class library will support specifications at the module
level. Further work will be done for supporting timing
The authors wish to acknowledge King Fahd University of
Petroleum and Minerals for utilizing the various facilities
in preparation and presentation of this paper.
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