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International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

828

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Manoj Mohapatra, Dept. of computer science and engineering,

National institute of Technology, Durgapur, India. +91-9734287730,

manoj.mhpt@gmail.com

Introducing Universal QCA Logic Gate for Synthesizing

Symmetric Functions with Minimum Wire-Crossings

ABSTRACT

This work introduces a universal Quantum-Dot Cellular Automata

logic gate (UQCALG) for synthesizing symmetric functions with

the target to reduce wire crossings in a design as well as the

number of operating clock cycles. It is realized with the coupled

majority-minority gate (CMVMIN) structure. The proposed

UQCALG structure not only improves performance of a QCA

design in terms of wire crossings and clocking, but also the

simultaneous access to its four outputs ensures the cost-effective

implementation of functions that may not be possible with that of

conventional universal logic gates.

Categories and Subject Descriptors

B.7.1 Integrated circuits

General Terms

Design, Performance, Verification Experimentation.

Keywords

Quantum-dot cellular automata, ULG, Universal QCA, Coupled

majority-minority gate and Symmetric functions.

1. INTRODUCTION

The QCA (Quantum-dot Cellular Automata) [1],[2],[4] is

considered to be a promising technology for future generation

ICs. The fundamental unit of QCA based design is the 3-input

majority gate. Since majority gate itself is not functionally

complete, majority gate and the inverter (MI) [2] are convention-

ally used for QCA logic design. The design with the universal

gate structures such as AOI (and-or-inverter) [12], NNI (nand-

nor-inverter) [3] and the CMVMIN gate [13] have also been

proposed. Realization of QCA devices has been reported in [1],

[6]. The focus on molecular implementations [5], [10] is the

recent development in QCA manufacturing.

Besides wide acceptance of QCA in logic design, it has become

an utmost necessity to permit least number of wire crossings in

QCA circuits due to its single layer restriction [15]. Minimum

wire crossings improve the buildability of a QCA layout. However

an MI based optimal design may not be optimal in terms of wire-

crossings. A ULG is, therefore, proposed in [15] to address this

issue.

Synthesis of symmetric Boolean functions on the other hand is

important in the sense that these play a key role in cryptology [16]

and, therefore, receiving a considerable attention. A number of

techniques to synthesize symmetric functions have been reported

in [7], [8]. Implementation of totally symmetric Boolean functions

around Quantum-Dot Cellular Automata has also been reported in

[9]. The two output CMVMIN (Coupled Majority-Minority) gate

based implementation of symmetric functions is demonstrated in

[13]. Such an implementation is simple and quashes the

requirement of disparate hardware, leading to an area saving

implementation.

The above scenario motivates us to introduce a Logic Gate

(UQCALG) structure that can realize universal functionality in its

outputs and then to investigate the effectiveness of the UQCALG

in realizing the symmetric functions. It targets reduced wire

crossings as well as clocking in a design. The next section

provides the basics of QCA. The UQCALG is introduced in

Section III. QCA implementation of symmetric functions, realized

with UQCALG, is reported in Section IV.

2. THE QCA BASICS

A quantum dot is a region where an electron can be quantum

mechanically confined (Figure.1(a)). A quantum cell consists of

four such quantum dots at each corner of a square and contains

two electrons. The electrons can quantummechanically tunnel

among the dots and settle (Figure.1(b)) either in polarization P=-1

(logic 0) or in P=+1 (logic 1).The basic structure realized with

QCA is the 3-input majority gate (MV (A,B,C) = maj (A,B,C) =

AB + BC + CA (Figure.2)). The 5-input AOI (And-Or-Inverter)

gate [12] has also been proposed to realize universal gate

function. In [3], we propose NNI gate as the basic logic element

for QCA based design. This 3-input gate realizes the function

F=NNI(A,B,C) = maj (A’, B, C’) = A’B + BC’+C’A’. In QCA

Permission to make digital or hard copies of all or part of this work for

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ICWET’10, February 26–27, 2010, Mumbai, Maharashtra, India.

Copyright 2010 ACM 978-1-60558-812-4…$10.00.

B Sen

Dept. of Computer Science and

Engineering, National Institute of

Technology, Durgapur,

WB, India

+91-9775774508

bibhash.sen@gmail.com

M Dalui

Dept. of Computer Science

and Engineering, Haldia

Institute of Technology, Haldia,

WB, India

+91-9433674096

mamata.06@gmail.com

B K Sikdar

Dept. of Computer Science and

Technology, Bengal Engineering

and Science University, Howrah

WB, India

+91-9830179574

biplab@cs.becs.ac.in

International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

829

Figure 1: QCA Cell

Figure 2: A Majority Gate

Figure

3: Wire Crossings

Figure 4: A CMVMIN Gate

based logic implementation, two kinds of QCA wires are possible.

The only allowable wire crossing in a QCA based design is shown

in Figure 3. It requires two different orientations, a 90 degree and

a 45 degree cell structure. However, manufacturing nano-scale

cells with two orientations is a challenging task.

The proposed Universal QCA logic gate is developed utilizing the

structure of a CMVMIN gate proposed in [13]. The CMVMIN

QCA gate structure simultaneously realizes 3-input minority logic

and majority voter (MV) in its 2 outputs F1 and F2 (Figure 4).

The F1 = A’B’ +B’C’ +C’A’ is the complement of F2 = AB + BC

+ CA. It ensures cost effective QCA logic design and also

realizable with a 3×3 tile structure [13]. The truth table of MV-

MIN gate is shown in Table I.

3. UNIVERSAL QCA LOGIC GATE

The gate which can implement any n-variable function is known

as the n-variable universal logic gate (n-ULG). The proposed

universal logic in [10] realizes the function

f(x,y,z) = xy + x’z’

3.1 UQCALG using CMVMIN gate structure

The CMVMIN gate of Figure 4 can function as an AND-NAND

gate (F2=AB and F1=(AB)') when input C is set to logic 0 and as

OR-NOR gate (F2=A+B and F1=(A+B)') when C is set to 1 [13].

To realize the universal logic as in ULG, 3 CMVMIN gates are

coupled as shown in Figure 5. It realizes,

UQCALG(y, x, z) = xy+x’z’ =

CMVMIN F2 (CMVMIN F2(y, 0, x), 1, CMVMIN F1(x, 1, z).

During implementation of the universal logic, 3 additional outputs

are generated from the proposed UQCALG structure. These

(except output-F4 of Figure.5) also realize the universal

functions.

International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

830

Figure 5: Universal QCA Logic Gate

(UQCALG)

Figure 6: UQCA Layout

Figure 7: Simulation result of UQCALG

Table II expresses the functionality of all the four functions of a

UQCALG.

The 3 variable-ULG reported in [15] takes four clock zones, three

majority gates, one inverter gate and three wire crossings, whereas

the UQCALG operates on three clock cycles and requires three

CMVMIN gates without any wire-crossing. The layout of the gate

is shown in Figure.6 and the simulation output of QCADesigner

[11] is in Figure.7.

3.2 QCA circuit design with UQCALG

In this section, we report design of a full adder and a 4-to-1

multiplexer using UQCALG. In case of multiplexer, we need to

use only 3 UQCALGs.

MUX4-1(A,B,C,D)=UQCALG-F2(UQCALG-F2(D,Y,C'),

X,UQCALG-F1(B,Y,A'))

where X and Y are the select lines (Figure 8). The final output

appears after 2 clock delays. The implementation requires only

204 cells realizing 3 UQCALGs without any wire-crossing.

Compared to MI and ULG based designs as in [15], UQCALG

based implementation achieves minimum reduction in terms of

number of wire crossings. Similar analysis is done for full adder

circuit also. The comparison between MI, ULG [15] and the

UQCALG based design is shown in Table III. A UQCALG based

design reduces wire crossings significantly in comparison to MI

or ULG based designs (Figure 9). It is also important to note that

831

Figure 8: Multiplexer realized with UQCA logic

gate

Figure 9: Comparison of different design paradigm

Figure 10: Two and three variable symmetric functions

the UQCALG based design takes lesser number of cells and clock

cycles.

4. SYNTHESIS OF SYMMETRIC

FUNCTION

The symmetric functions are receiving considerable attention from

the researchers working in the field of VLSI design, specially for

logic synthesis [7], [8]. A number of synthesis techniques for

Boolean symmetric functions are reported. We present a cost

effective design of symmetric function realized with the

UQCALG introduced in the earlier section.

4.1 The symmetric function

A vertex (minterm) is a set of variables in which each variable

appears only once. The weight w of a vertex v is the number of

uncomplemented variables appeared in v. A switching function

f(x1,x2,….xn) is called totally symmetric with respect to the

variables x1,x2,….xn, if it is invariant under any permutation of

the variables. Total symmetry can be specified by a set of

integers(called a-numbers) A = (a1,… ,aj,.., ak), where A

0, 1,

2,...,n. All the vertices with weight w

A will appear as true

minterms in the function.

An n-variable symmetric function is denoted as Sn(a1,… ,aj,.., ak).

A symmetric function is called consecutive, if the set A consists of

only consecutive integers (al, al+1,…., ar). It is expressed as Sn(al-

ar), where l < r. For n variables, there can be 2n+1 - 2 different

symmetric functions (excluding constant functions 0 and 1). Each

totally symmetric function Sn(A) can be expressed uniquely as a

union of maximal consecutive symmetric functions, such that

Sn(A) = Sn(A1)+Sn(A2)+……+Sn(Am), where m is minimum,

i,

j, l

i, j

m, Ai

Aj=

and i < > j.

Example 1: There can be in total Sn= (2n+1 - 2) symmetric

functions. For n=2, it is S2= 22+1 - 2 = 6. The functions are A'B',

AB, A+B, A'+B', A'B+AB', AB+A'B'. Similarly, there are S3=

23+1 - 2 = 14 three-variable symmetric functions. The functions

are shown in Figure 10.

Example 2: The symmetric function S12(1, 2, 5, 6, 7, 9, 10) can be

expressed as S12(1-2)+S12(5- 7)+S12(9-10), where S12(1-2); S12(5-

7) and S12(9-10) are the maximal consecutive symmetric

functions.

4.2 UQCALG realization of symmetric

function

Though the universal gate structure introduced in this work is

useful for designing any arbitrary logic circuit, the more effective

832

Figure11: UQCALG based realization of 2-variable

symmetric functions

Figure 12: Performance of UQCALG in realizing

2-variable symmetric functions

use can be for the cases where most of the four outputs of

UQCALG are utilized simultaneously. In this section, we explore

realization of symmetric functions to illustrate the effectiveness of

UQCALG. A realization of 2-variable symmetric functions is

shown in Figure 11. It utilizes 9 outputs of the 3 UQCALG while

implementing the six 2-variable symmetric functions. The

unutilized 3 outputs are the garbage outputs. The effectiveness of

UQCALG based realization is compared with the existing QCA

designs, in terms of number of wire crossings and gate count, in

Figure 12. The number of wire crossings in UQCALG based

implementation is 0 whereas, it is 2 for ULG [15] based design

and 4 in MV-INV implementation. It can also be observed that

the proposed UQCALG implementation is most area saving

(requires 3 gates) than that of the ULG [15] (7 gates) and MV-

INV (8 gates) based implementations. Figure 13 describes QCA

realization of both the 2 and 3 variable symmetric functions to

demonstrate the better utilization of the UQCALG outputs. The

implementation as a whole requires only 9 wire crossings and 11

gates that can not be achievable with the MV-INV or ULG [15].

5. CONCLUSIONS

This work introduces a universal QCA logic gate for synthesizing

symmetric functions in QCA platform. It is designed with the

basic CMVMIN (Coupled majority-minority) gate structure

proposed in [13]. The UQCALG based realization of symmetric

function results in a cost-effective design in terms of number of

wire crossings as well as the number of operating clock cycles.

6. ACKNOWLEDGMENTS

This work is supported by the Sponsored Cellular Automata

Research Projects, Bengal Engineering and Science University,

Shibpur, WB, India - 711103.

7. REFERENCES

[1] A. O. Orlov, I. Amlani, G.H. Bernstein, C.S. Lent and G.L.

Snider, ‘Realization of a functional cell for quantum-dot

cellular automata’, Science, Vol. 277, pp. 928-930, 1997.

[2] A. O. Orlov, I. Amlani, G. Toth, C.S. Lent, G.H. Bernstein

and G.L. Snider, ‘Digital logic gate using quantum-dot

cellular automata’, Applied Physics Letters, Vol. 74, pp. 2875,

1999.

[3] B.Sen and B.K. Sikdar, ‘Characterization of universal Nand-

Nor-Inverter QCA gate’, in Proceedings of 11th IEEE VLSI

Design and Test Symposium, Kolkata, pp. 433-442, Aug

2007,.

[4] C.S. Lent, P.D. Taugaw, W. Porod and G.H. Bernstein,

‘Quantum cellular automata’, Nanotechnology, Vol. 4, pp.

49-57,1993.

[5] C.S. Lent, B. Isaksen and M.Lieberman, ‘Molecular quantum-

dot cellular automata’, J. Amer. Chem. Soc., Vol. 125, pp.

1056-1063, 2003.

[6] D. Berzon and T.J. Fountain, ‘ A memory design in QCAs

using the SQUARES formalism’, in Proceedings of Great

Lakes Symposium on VLSI, pp. 166-169, 1999.

[7] D.L.Dietmeyer, ‘Generating minimal covers of symmetric

function’, IEEE TCAD, Vol. 12, no. 5, pp. 710-713, May

1993.

[8] H. Rahman. D.K. Das and B.B. Bhattacharya, ‚Mapping

symmetric functions to hierarchical modules for path-delay

fault testability’, Proceedings, Asian Test Symposium (ATS),

IEEE CS Press, USA, pp. 284-289, Nov. 2003.

[9] H. Rahman, B.K. Sikdar and D.K. Das, ‘Synthesis of

Symmetric Functions Using Quantum Cellular Automata’,

IEEE DTIS, Tunis, Tunisia, Sept 2006.

[10] J. Huang, M. Momenzadeh, L. Schiano anf F. Lombardi.

‘Simulation-based design of modular QCA circuits’, IEEE

conference on nanotechnology, Nagoya, 2005.

[11] K. Walus et. al., ‘ATIPS laboratory QCADesigner

homepage’, http://www.atips.ca/projects/qcadesigner,

ATIPS laboratory. Univ. of Calgary, Canada, 2002.

833

Figure 13: UQCALG based implementation of 2 and 3 variable symmetric

functions

[12] M.B. Tahoori, J.Huang, M.Momenzadeh and F. Lombardi,

Characterization, test and logic synthesis of And-Or-Inverter

(AOI) gate design for QCA implementation’, IEEE TCAD,

Vol. 24, No 12, December 2005; pp. 1881-1893.

[13] S. Ditti, P.K. Bhattacharya, P. Mitra and B.K. Sikdar ‘Logic

Realization with Coupled QCA Majority-Minority Gate’,

VDAT,2008.

[14] X.X. Chen, X.W. Wu, ‘Modern digital theory’, in Zhejiang

University Press, 2001.

[15] Yinshui Xia and Keming Qui ‘Design and application of

Univarsal logic based on Quantum-dot Cellular Automata’,

in Proceedings of 11th IEEE conference on Communication

Technology, 2008.

[16]Y.X. Yang and B.Guo, ‘Futher Enumerating Boolean

Functions of cryptographic significance’, J.Cryptology, Vol.

8, No. 3, pp. 115-122, 1995.