Conference Paper

Instrumenting where it hurts: An automatic concurrent debugging technique

DOI: 10.1145/1273463.1273469 Conference: Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2007, London, UK, July 9-12, 2007
Source: DBLP


As concurrent and distributive applications are becoming more common and debugging such applications is very dif- ficult, practical tools for automatic debugging of concurrent applications are in demand. In previous work, we applied automatic debugging to noise-based testing of concurrent programs. The idea of noise-based testing is to increase the probability of observing the bugs by adding, using instru- mentation, timing "noise" to the execution of the program. The technique of finding a small subset of points that causes the bug to manifest can be used as an automatic debugging technique. Previously, we showed that Delta Debugging can be used to pinpoint the bug location on some small pro- grams. In the work reported in this paper, we create and evaluate two algorithms for automatically pinpointing program loca- tions that are in the vicinity of the bugs on a number of in- dustrial programs. We discovered that the Delta Debugging algorithms do not scale due to the non-monotonic nature of the concurrent debugging problem. Instead we decided to try a machine learning feature selection algorithm. The idea is to consider each instrumentation point as a feature, execute the program many times with dierent instrumen- tations, and correlate the features (instrumentation points) with the executions in which the bug was revealed. This idea works very well when the bug is very hard to reveal using instrumentation, correlating to the case when a very specific timing window is needed to reveal the bug. However, in the more common case, when the bugs are easy to find using in- strumentation (i.e., instrumentation on many subsets finds the bugs), the correlation between the bug location and in- This work is partially supported by the European Com- munity under the Information Society Technologies (IST) programme of the 6th FP for RTD - project SHADOWS contract IST-035157. The authors are solely responsible for the content of this paper. It does not represent the opinion of the European Community, and the European Community is not responsible for any use that might be made of data appearing therein. strumentation points ranked high by the feature selection algorithm is not high enough. We show that for these cases, the important value is not the absolute value of the evalua- tion of the feature but the derivative of that value along the program execution path. As a number of groups expressed interest in this research, we built an open infrastructure for automatic debugging al- gorithms for concurrent applications, based on noise injec- tion based concurrent testing using instrumentation. The infrastructure is described in this paper.

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    • "We have implemented data race and atomicity violation detection tool based on AtomRace algorithm. The tool is implemented in Java on top of ConTest [4]a concurrency testing tool which provides us with a listeners architecture [20], static bytecode instrumentation, and noise injection heuristics [27]. Our static analyses are implemented in "
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    ABSTRACT: The paper proposes a novel algorithm called AtomRace for a dynamic detection of data races. Data races are detected as a special case of atomicity violations on atomic sections specially defined to span just particular read/write instructions and the transfer of control to and from them. A key ingredient allowing AtomRace to efficiently detect races on such short atomic sections is a use of techniques for a careful injection of noise into the scheduling of the monitored programs. The approach is very simple, fully automated, avoids false alarms, and allows for a lower overhead and better scalability than many other existing dynamic data race detection algorithms. We illustrate these facts by a set of experiments with a prototype implementation of AtomRace. Further, AtomRace can also be applied to detect atomicity violations on more general atomic sections than those used for the data race detection. They can be defined by the user or obtained by some static analysis.
    Full-text · Conference Paper · Jan 2008
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    • "Thus, many small subsets of instrumentations reveal the bug. Despite this fact, DD was unable to find minimal instrumentation [25], which is the goal of the debugging algorithm. The third program we used is an example of a buffer overflow and underflow in a standard producer-consumer program. "
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    ABSTRACT: Concurrent computer programs are fast becoming prevalent in many critical applications. Unfortunately, these programs are especially difficult to test and debug. Recently, it has been suggested that injecting random timing noise into many points within a program can assist in eliciting bugs within the program. Upon eliciting the bug, it is necessary to identify a minimal set of points that indicate the source of the bug to the programmer. In this paper, we pose this problem as an active feature selection problem. We propose an algorithm called the iterative group sampling algorithm that iteratively samples a lower dimensional projection of the program space and identifies candidate relevant points. We analyze the convergence properties of this algorithm. We test the proposed algorithm on several real-world programs and show its superior performance. Finally, we show the algorithms' performance on a large concurrent program.
    Full-text · Conference Paper · Jan 2008
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    ABSTRACT: A recent trend of transitioning to multicore architectures in the mainstream market segments creates significant challenges for programming systems. The market need for creating portable multithreaded applications that exploit high performance of chip multiprocessors is not easily supported by existing programming models and languages, compiler technology, performance analysis and testing tools. We overview various research directions in this area and present some partial results achieved by the industry. The computer architecture world is going through a significant change in the past several years. Since the eighties and nineties of the last century, based on the Moore law formulation new generations of superfast processors were coming out every 18 to 24 months, where the new version of hardware had the clock rate usually twice or even more faster than the previous one. So the focus of the computer architects and the compiler people at that time was merely on how to increase the Instruction Level Parallelism (ILP), both in the processor hardware and the compiler optimization techniques and also combination of both. Though it appeared very soon that more and more cycles are being spent not in the processor core execution, but in the memory subsystem which includes the multilevel caching structure, and the so-called Memory Wall problem started to evolve quite significantly due to the fact that the increase in memory speed didn't match that of processor cores. More importantly, a few years ago a new evidence came out showing that it's very hard and not economical to speed the processor clock further due to tremendous increase in power consumption and power dissipation by the advanced computer systems. This phenomenon received the name of the Power Wall problem, and the net result is that most of the industrial manufacturers of advanced processors such as Intel, AMD, Sun and IBM ceased coming out with ever increased clock rate processors and started to consider for alternative ways of providing increased performance in their computer offerings. Very soon a new direction for increasing the overall performance of computer systems had been proposed, namely changing the structure of the processor subsystem to utilize several processor cores on a single chip. These new computer architectures received the name of Chip Multi Processors (CMP) and allowed to provide increased performance for new generation of systems, while keeping the clock rate of individual processors cores at a reasonable level. The result of this architectural change is that it is possible to provide further improvements in performance while keeping the power consumption of the processor subsystem almost constant, the trend which appears essential not only to power sensitive market segments such as embedded systems, but also to computing server farms which suffer of power consumption/dissipation problems as well. One can argue that the exploitation of multiple processors in computer systems was known already for several decades, but the claim is that in the past it was merely limited to very expensive high-performance systems (HPC) or very specialized embedded offerings which were based on a collection of DSPs. These days, almost every regular desktop or mobile computer you can buy in a store near you will most likely include several processor cores inside their box, not talking about powerful server farms and sophisticated game consoles such as Xbox 360 or Playstation 3. So, the accelerated trend is that CMPs are pervasive in almost every segment of the market, and the question is what does it mean to the hardware and software parts of the computer industry? The focus of this overview paper is on how CMPs affect the software development processes, i.e. how we program for multicore architectures, how we test and evaluate the performance of multithreaded applications, etc.
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