Conference Paper

Low power integrated scan-retention mechanism

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
DOI: 10.1145/566408.566436 Conference: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002
Source: DBLP


This paper presents a methodology for unifying the scan mechanism and data retention in latches which leads to scannable latches with the data retention capability achieved at a very low power overhead during the active mode. A detailed analysis of power and area overhead is presented, with layout examples for various common latch styles. Implications of using different power gating techniques for reducing leakage during sleep mode on the design of retention latches are considered, including well biasing for leakage control and sharing wells between gated logic and retention latch devices.

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Available from: Stephen Kosonocky, May 22, 2014
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    • "The flops implement a single clock pin for function and test mode clocking. This simplifies clock distributions and reduces power on the pulse clock tree compared with three clocks implemented in the scan-latch based retention pulsed flops reported in [24]. An efficient retention circuit has been designed in the proposed flops with very low overhead using a single retention control signal instead of dual " save " and " restore " signals used in the balloon-style retention flops. "
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    ABSTRACT: This paper presents two area and power-delay efficient state retention pulsed flops with scan and reset capabilities for sub-90 nm production low-power designs. The proposed flops also mitigate area overhead and integration complexity in SoC designs by implementing a single retention control signal and shared function/scan mode clock.
    Preview · Conference Paper · Nov 2008
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    • "This can be alleviated by employing an interface circuit with the capability of preserving the logic during standby mode. As storage elements lose their states in standby mode, alternative elements, which are capable of state retention, must be used [1], [4], [5]. Sizing of the current switch is critical in terms of performance, area, and leakage current [6]. "
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    ABSTRACT: The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.
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    • "If a small minimum power-down time is required, a local storage of internal data is necessary. Static state-retention flipflops (SSRFF), which preserve their content even if the power supply of the circuit block is cut off, have been proposed [1], [4], [5], [7]. The basic principle is shown in Fig. 2. A high threshold latch either within [4] or in parallel [5] to the signal path is supplied by a constant supply voltage. "
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    ABSTRACT: Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps
    Preview · Article · Aug 2006 · IEEE Journal of Solid-State Circuits
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