A Low-Power Design Methodology for High-Resolution
Pipelined Analog-to-Digital Converters
Reza Lotfi Mohammad Taherzadeh-Sani M.Yaser Azizi Omid Shoaei
IC-Design Lab., ECE Dept., University of Tehran,
North Kargar Ave., Tehran, I.R.Iran
In this paper a general method to design a pipelined ADC with
minimum power consumption is presented. By expressing the
total static power consumption and the total input-referred noise
of the converter as functions of the capacitor values and the
resolutions of the converter stages, a simple optimization
algorithm is employed to calculate the optimum values of these
parameters, which lead to minimum power consumption while a
specified noise requirement is satisfied. To determine the bias
current values of operational amplifiers, a novel optimal choice
for settling and slewing time parameters is proposed applicable to
both single-stage and two-stage Miller-compensated opamp
structures. Using the proposed methodology, the optimum values
for capacitors, the resolutions and the opamp device sizes of all
stages are determined in order to minimize the total power
consumption. Design examples are presented and compared with
conventional approaches to show the effectiveness of the
Categories and Subject Descriptors
B.7.1 [Integrated circuits] Types and Design Styles VLSI (very
large scale integration)
Low-Power Design, Pipelined Analog-to-Digital Converters,
Pipelining is one of the best approaches to implement high-speed
low-power analog-to-digital converters. Design approaches to
reduce the power consumption of pipelined ADCs are therefore of
great importance to realize medium-to-high resolution high-speed
A/D converters with the least possible power consumption.
Several approaches have been proposed in literature for
systematic design of pipelined A/D converters. In  it has been
concluded that to minimize the power consumption of a pipelined
S/Hm1 bitsm2 bitsm3 bits2 bits
DIGITAL ERROR CORRECTION
Figure 1. The pipeline ADC structure
ADC, the resolution of all the stages can be chosen equal to 1.5
just in converters with resolutions of less than 10 bits. In  a
systematic design methodology has been proposed where
resolutions higher than 1.5 have been proposed for the front-end
stages of the high-resolution converters but the capacitor values of
the stages are not optimized and a predefined noise distribution is
assumed. In  the effects of the capacitor scaling, parallelism,
and non-identical resolutions per stages on the pipelined ADC
power consumption are investigated separately. In the latest
reported automatic design tool for pipelined ADCs  the
converter is optimized to minimize the power consumption and
area using geometric programming. However, the latter algorithm
is applied to a converter with identical resolution per stages. As
far as we understood it appears that neither of the proposed
approaches are as general yet simple as the approach proposed in
In this paper with no specific constraint, arbitrary capacitor
scaling as well as non-identical resolution per each stage is
utilized in the design of the converter as shown in Fig. 1.
Effective equations are presented to optimally determine the
capacitor value and the resolution of each stage, in order to
minimize the power consumption of the converter, which makes
use of operational trans-conductance amplifiers (OTAs) with
optimized settling and slewing times.
First, a closed-form equation for the bias current value of a single-
stage or two-stage Miller-compensated opamp is derived
employing an innovative dynamic allocation of the small- and
large-signal settling time parameters. Then the total static power
dissipation of the pipelined ADC is calculated. In section 3, the
total input-referred noise of the converter is derived. Then a
design methodology is presented to minimize the power
consumption with a defined signal-to-noise ratio (SNR). The
input parameters of the optimization CAD tool and related
considerations are addressed. Finally optimization examples
confirming the efficiency of the proposed methodology are
presented and the dependency of the power consumption on the
specifications of the converter is investigated.
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stages are used. It can be observed that by adding one bit to the
overall resolution, the current consumption is increased with a
higher rate in higher resolutions. This is mainly due to the fact
that in low resolutions the capacitor values are mainly determined
by the required matching rather than the kT/C noise. However at
higher resolutions the thermal noise determines the capacitor
values. When the resolution is increased by a single bit, the
magnitude of the LSB voltage is halved and the thermal noise
power should become one fourth. Thus the capacitor values are to
become four times larger. From (15) it can be concluded that the
OTA contributions in the total current consumption becomes
approximately four times larger however the number of
comparators is not multiplied by four. Hence the total current is
increased by a factor less than four. The dependency of the power
dissipation on the full-scale voltage can be also investigated as
shown in Fig. 6 for a 12-bit 50MS/s example. It can be seen that if
the full-scale voltage is halved, the current consumption is
increased by a factor of more than two. This behavior can be
clearly predicted from the optimized value for the current
consumption given by (9) keeping in mind the dependency of
Cload on the full-scale voltage. Therefore the power consumption
of the ADC increases by scaling down the voltage.
The optimized value for the current consumption of a single-stage
OTA or a two-stage Miller-compensated OTA, was obtained
assuming that the second pole frequency is larger than the unity-
gain frequency of the amplifier not to degrade the frequency
response. However it is obvious that this assumption is not always
the case when the non-dominant poles are not large enough to be
neglected. This fact affects not only the settling behavior but also
the thermal noise equivalent bandwidth of the OTA. This non-
ideal settling time can be shown to be smaller than what predicted
by (3), therefore the problem has been overestimated here. The
noise behavior is overestimated as well since the noise equivalent
bandwidth of the OTA is smaller than what predicted by (20) if
the second pole is not located much higher than the unity-gain
The non-ideal frequency response
In this paper based on a novel approach to design the operational
amplifier in a switched-capacitor circuit, a closed-form equation
for the total optimized current of a pipelined ADC is presented.
Besides, considering the noise sources in a residue-amplifier, a
closed-form relation for the total input-referred thermal noise of
the ADC is derived as well. Based on the developed equations an
efficient design methodology for pipelined A/D converters is
developed. The proposed approach can simultaneously determine
the capacitor values and the resolutions of the residue stages of
the converters with no limiting assumption. Design examples are
presented to verify the effectiveness and the generality of the
proposed methodology. It has been shown that the developed
CAD tool can be even employed to decide about the architecture
of the comparators or the optimum value for the reference voltage.
The dependency of the current dissipation of the ADC on some of
the converter specifications has been investigated as well to
illustrate the usefulness of the presented equations.
789 10 11 1213 14
The converter Resolution (bits)
Total Current Consumption (mA)
consumption of the 50MS/s converter on the resolution
Dependency of the optimized current
0 0.51 1.52 2.5
Reference voltage (V)
Total current consumption (mA)
Figure 6. Dependency of the optimized current consumption
of the 12-bit 50MS/s converter on the full-scale voltage swing
 S.H. Lewis, “Optimizing the stage resolution in pipelined,
multistage, analog-to-digital converters for video-rate
applications,” IEEE Trans. Circuits &Systems-II, Vol.39,
No.8, pp.516-523, Aug. 1992.
 J.Goes, et.al, “ Systematic design for optimization of high-
speed self-calibrated pipelined A/D converters,” IEEE
Trans. Circuits & Systems-II, vol.45, pp.1513-26, Dec. 98.
 P.T.F. Kwok, H.C.Leung, “Power optimization for pipeline
analog-to-digital converters,” IEEE Trans. On Circuits &
Systems-II, vol.46, pp.549-53, May 1999.
 M. Hershenson, “Design of pipeline analog-to-digital
converters via geometric programming,” Proc. of IEEE Intl.
Conf. on Computer Aided Design, 2002.
 M. Waltari, Circuit techniques for low-voltage and high-
speed A/D converters, PhD. Dissertation, Helsinki Univ. of
 B. Razavi, Design of Analog CMOS Integrated Circuits,
 K. Bult, G. Geelen, “A fast-settling CMOS opamp for SC
circuits with 90-dB DC gain” in IEEE Journal of Solid-State
Circuits, vol.25, pp.1379-84, Dec. 1990.
 S.Rabii, B.Wooley, “A 1.8-V digital-audio sigma-delta
modulator in 0.8-um CMOS,” in IEEE Journal of Solid-
State Circuits, vol.32, pp.783-796, Jun.1997.
 T. Cho, Low-power
conversion techniques using pipelined architectures, PhD.
Thesis, University of California, Berkeley, 1995.
 A. Abo, P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS
pipeline analog-to-digital converter,” in IEEE Journal of
Solid-State Circuits, vol.30, pp.166-172, Mar.1995.
 I. Mehr, L. Singer,”A 55-mW, 10-bit, 40-MSample/s
nyquist-rate CMOS ADC,” in IEEE Journal of Solid-State
Circuits, vol.30, pp. 318-325, Mar.2000.