Conference Paper

A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding

Technische Universität Kaiserslautern, Kaiserlautern, Rheinland-Pfalz, Germany
DOI: 10.1109/SIPS.2006.352570 Conference: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada
Source: DBLP


Future mobile and wireless communications networks require flexible modem architectures with high performance. This paper presents a dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel coding in wireless communications systems: FlexiTreP. It features Viterbi and Log-MAP decoding for support of binary convolutional codes and binary as well as duobinary turbo codes. The FlexiTreP can support more than 10 current wireless communication standards. Furthermore, its flexibility allows for adaptation to future systems. It consists of a specialized pipeline and a dedicated communication and memory infrastructure. Simulation and synthesis results obtained for Log-MAP and Viterbi applications demonstrate maximum throughput of 200 and 133 Mbps, respectively

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    • "Depending upon the coupling of the fabric 1 to the core processor, there are two architectural categories of reconfigurable multi-core processors (as shown in Fig 1): (a) Reconfigurable multi-core processors with a dedicated fabric (Fig 1a) comprise core processors and their individual fabrics. An example is RAMPSoC [1] where each core represents a reconfigurable instruction-set processor (e.g., [2] or [3]). However, such an architecture , scenarios may arise where one core fully utilizes its fabric (and probably could require even more than that), while another core may only partially or not at all use its fabric. "
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    ABSTRACT: A novel policy for allocating reconfigurable fabric resources in multi-core processors is presented. We deploy a Minority-Game to maximize the efficient use of the reconfigurable fabric while meeting performance constraints of individual tasks running on the cores. As we will show, the Minority Game ensures a fair allocation of resources, e.g., no single core will monopolize the reconfigurable fabric. Rather, all cores receive a “fair” share of the fabric, i.e., their tasks would miss their performance constraints by approximately the same margin, thus ensuring an overall graceful degradation. The policy is implemented on a Virtex-4 FPGA and evaluated for diverse applications ranging from security to multimedia domains. Our results show that the Minority-Game policy achieves on average 2× higher application performance and a 5× improved efficiency of resource utilization compared to state-of-the-art.
    Full-text · Conference Paper · Mar 2011
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    • "The K-best LSD processor used in this paper is presented in detail in [25]. Turbo decoder can be implemented, for example, as a coprocessor of a DSP as in [26] or a hardware accelerator [27] or an ASP [28]. Naturally, there are variants of the algorithm, and the level of parallelism and clock frequency mainly determine the throughput. "
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    ABSTRACT: Data rates in the upcoming 3G long term evolution (LTE) standard will be manifold when compared to the current universal mobile telecommunications system. Implementing receivers conforming with the high-capacity transmission techniques is challenging due to the complexity and computational requirements of algorithms. In this study, the software defined radio (SDR) is targeted and the four essential baseband functions of the 3G LTE receiver, namely, list sphere decoding, fast Fourier transform, QR decomposition, and turbo decoding, are addressed and the functions are implemented as application specific processors (ASPs). As a result, the design space that describes the essential computational challenges of 3G LTE receivers is clarified and estimates of area, power, and interprocessor communication buffer requirements are presented.
    Full-text · Article · Feb 2009 · International Journal of Digital Multimedia Broadcasting
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    ABSTRACT: Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.
    Full-text · Article · Feb 2009 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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