Conference Paper

Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports

DOI: 10.1007/978-3-540-74442-9_8 Conference: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Source: DBLP


A low-power content addressable memory (CAM) with read/write and mask match ports is proposed. The CAM cell is based on the
conventional 6T cross-coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In
addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out
port exploits a pre-charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing
amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read
and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed
using 0.18-μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage.

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