Conference Paper

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits

DOI: 10.1007/978-3-540-74442-9_15 Conference: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Source: DBLP


The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental ∞uctuations. Modern circuit designs may,sufier from design uncertainties, unpredictable in the design phase or even after manufacturing. This paper presents an optimization technique to make pipeline circuits robust against delay variations and thus maximize timing yield. By trading larger ∞ip-∞ops for smaller latches, the proposed approach can be used as a post-synthesis or post-layout optimization tool, allowing accurate timing information to be available. Experimental results show an average of 31% timing yield improvement,for pipeline circuits. They suggest that our method,is promising for high-speed designs and is capable of tolerating clock variations.

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