Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.

Conference Paper · January 2011with13 Reads
DOI: 10.1109/FPL.2011.104 · Source: DBLP
Conference: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece

    Abstract

    The floor planning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floor planner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs.