High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices.

Conference PaperinLecture Notes in Computer Science · January 2002with1 Read
Impact Factor: 0.51 · DOI: 10.1007/3-540-46117-5_29 · Source: DBLP
Conference: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings


    This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital
    system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent
    partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations
    of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of
    this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the
    physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between
    vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments.