Very high speed 17 Gbps SHACAL encryption architecture

Conference PaperinLecture Notes in Computer Science 2778:111-120 · September 2003with10 Reads
Impact Factor: 0.51 · DOI: 10.1007/978-3-540-45234-8_12 · Source: DBLP
Conference: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings


    Very high speed and low area hardware architectures of the SHACAL-1 encryption algorithm are presented in this paper. The
    SHACAL algorithm was a submission to the New European Schemes for Signatures, Integrity and Encryption (NESSIE) project and
    it is based on the SHA-1 hash algorithm. To date, there have been no performance metrics published on hardware implementations
    of this algorithm. A fully pipelined SHACAL-1 encryption architecture is described in this paper and when implemented on a
    Virtex-II X2V4000 FPGA device, it runs at a throughput of 17 Gbps. A fully pipelined decryption architecture achieves a speed
    of 13 Gbps when implemented on the same device. In addition, iterative architectures of the algorithm are presented. The SHACAL-1
    decryption algorithm is derived and also presented in this paper, since it was not provided in the submission to NESSIE.