Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off

Conference Paper · April 2008with40 Reads
DOI: 10.1007/978-3-540-89853-5_26 · Source: DBLP
Conference: Wireless Networks, Information Processing and Systems, International Multi Topic Conference, IMTIC 2008, Jamshoro, Pakistan, April 11-12, 2008, Revised Selected Papers
Abstract
The delay of a circuit implemented in a Lookup table (LUT) based Field-Programmable Gate Arrays (FPGAs) is a combination of routing delays, and logic block delays. However most of an FPGA’s area is devoted to programmable routing. When these blocks are replaced with logic clusters, the fraction of delay due to the cluster has significant impact on total delay. This paper investigates the impact of logic cluster size when the most favorable LUT size is achieved. As a result, fast and area efficient FPGA architecture can be proposed that can combine the logic blocks into logic clusters. In lookup table FPGA architecture, area and delay are the main factors to be tackled, the best value for each of the parameters depends on complex trade-offs. If an FPGA with smaller LUTs is constructed to minimize the area, the result is poor speed. On the other hand, if an FPGA includes larger LUTs, speed might increase but area is unnecessarily wasted. In this experimental work 20 benchmark circuits were tested to calculate the delay and area metric. Results show increasing logic cluster size has no more effect on delay as well as area, when suitable optimal values of lookup table size (LUT) are established.
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