In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The
... [Show full abstract] reconfigurable design and testing are carried out on FPGA, the results showed that it is able to meet the high-performance information security systems encryption algorithm on the speed requirement.