A Low-Power Multithreaded Processor for Software Defined Radio

Journal of VLSI Signal Processing (Impact Factor: 0.73). 06/2006; 43(2-3):143-159. DOI: 10.1007/s11265-006-7267-1
Source: DBLP


Embedded digital signal processors for software defined radio have stringent design constraints including high computational
bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards
with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed
in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital
signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful
compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power
consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high
performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a
complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010
achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth,
GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for
a wide variety of digital signal processing and multimedia applications.

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    • "For example, X ′ 1 = [0] [1] [2] [3] [4] [5] [6] [7] "
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    ABSTRACT: Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.
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    • "Hence, prevelance in multiple standards and government requirements makes AES a useful protocol to accelerate. While much work has been done to show that sufficient baseband processing capabilities are available in SDRs [25], instruction set architecture (ISA) support for secure SDR has not been a focus of previous research. This paper prsents a hardware design and instruction set extensions for AES processing on a multithreaded SDR platform, the Sandbridge SB3010 System. "
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    ABSTRACT: Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current W-CDMA, GPS, GSM, and WiMAX applications can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50Mbps. Some of the fastest AES software im-plementations only achieve 20Mbps on our reference platform. In order to have secure software-defined radio, the security processing gap must be addressed. This paper presents instruction set architecture (ISA) extensions for the Sandblaster DSP. The Sandblaster DSP is a multithreaded processor for SDR that issues multiple operations each cycle and supports vector operations.
    Preview · Article · Aug 2010 · International Journal of High Performance Systems Architecture
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    • "Its kernel idea was MPP signal processing with many simple cores [6]. Researchers from Sandbridge, University of Wisconsin, and Delft University of Technology proposed sandblaster [7]. It effectively avoided pipeline stall through multi-threading. "
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    ABSTRACT: In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled Time Division Multiplexing Bus, with which programmers can easily explore memory-level parallelism of applications by proper instructions and scheduling algorithms. MPE, which is the kernel component of GAEA, adopts hybrid parallel processing scheme to explore instruction-level and data-level parallelism. The pipeline and instruction set of GAEA are also optimized for the next generation wireless communication systems. The evaluation and implementation results show that GAEA architecture is suitable for the next generation wireless communication systems.
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