Article

Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations

Synopsys, Inc., Mountain View
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Impact Factor: 1). 03/2008; 27(3):445-455. DOI: 10.1109/TCAD.2008.916341
Source: DBLP

ABSTRACT

This paper presents a novel gate-sizing methodology to minimize the leakage power in the presence of process variations. The method is based on modeling the statistics of leakage and delay as posynomials functions to formulate a geometric-programming problem. The existing statistical leakage model is extended to include the variations in gate sizes, as well as systematic variations. Using a simplified delay model, we propose an efficient method to evaluate the alpha-percentile of path delays without enumerating the paths in a circuit. The complexity of evaluating the objective function of the optimization problem is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. The statistical optimization methodology is shown to provide as much as 15% reduction in the mean leakage power as compared to traditional worst case gate sizing with the same delay constraints.

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    • "Leakage or static power is consumed all the time, i.e., even when the circuit is idle. It is unnecessary and one would like to eliminate it [3]. Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. "

    Full-text · Article · Oct 2012 · International Journal of Computer Applications
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    • "In the 180nm CMOS technology, these process variations have caused about 30% variation in chip frequency, along with 20x variation in current leakage [3]. Accordingly, a large number of chips with significantly high leakage have to be discarded, resulting in a considerable parametric yield loss [1]. Also, this magnitude of intra-die channel length variations has been estimated to increase from 35% of total variations in 130nm to 60% in 70 nm CMOS process, and variation in wire width, height, and thickness is also expected to increase from 25% to 35% [4]. "
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    ABSTRACT: Performance variation is one of the primary concerns in nanoscale CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in nanoscale CMOS circuits. The proposed algorithm is based on identifying the significance of timing paths in a design, and performing respective optimization for optimal design performance. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.
    Full-text · Article · May 2011 · Conference Record - IEEE Instrumentation and Measurement Technology Conference
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    • "In the 180nm CMOS technology, these process variations have caused about 30% variation in chip frequency, along with 20x variation in current leakage [7]. Accordingly, a large number of chips with significantly high leakage have to be discarded, resulting in a considerable parametric yield loss [3]. Also, this magnitude of intra-die channel length variations has been estimated to increase from 35% of total variations in 130nm to 60% in 70 nm CMOS process, and variation in wire width, height, and thickness is also expected to increase from 25% to 35% [8]. "
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    ABSTRACT: Performance variation is one of the primary concerns in nanometer-scale dynamic CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of significantly reducing worstcase delay, delay uncertainty, and delay sensitivity to process variations in dynamic CMOS circuits. The proposed algorithm is based on identifying the significance of all timing paths in the design, increasing the sizes of transistors that appear in most number of paths to reduce delays of most paths. In parallel, it minimizes the channel load by reducing the size of transistors in the interacting paths, which will lead to a power saving. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.
    Full-text · Conference Paper · Mar 2011
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