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Parameterization of efficient dynamic reconfigurable trees
Abstract
We present an algorithm for dynamic reconfiguration from a set of processor nodes connected using a multistage interconnection network into a set of m-ary trees of height h. The algorithm allows parameterization based on the branching factor m, the height of the tree h and bias B and produces a set of isomorphic trees for each value of the bias B. The computation of the identities of the neighbors by the nodes is performed using simple binary operations in parallel.
... All configurations have been used to address the problem of data transfer between processors shown in Table 3 [19]. ...
... Then, the total time required to perform the whole job is equal 390, (100+150+60+80=390). The time to perform the same problem by the best but not optimum tree constructed in [19] is also one of the configurations achieved by GA, and represented in Table 5 (C20) was 1430. Hence, there is a performance improvement of 370% using Genetic Algorithm. ...
Dynamic architectures have emerged to be a promising implementation platform to provide flexibility, high performance, and low power consumption for computing devices. They can bring unique capabilities to computational tasks and offer the performance and energy efficiency of hardware with the flexibility of software. This paper proposes a genetic algorithm to develop an optimum configuration that optimizes the routing among its communicating processing nodes by minimizing the path length and maximizing possible parallel paths. In addition, this paper proposes forward, virtually inverse, and hybrid data exchange approaches to generate dynamic configurations that achieve data exchange optimization. Intensive experiments and qualitative comparisons have been conducted to show the effectiveness of the presented approaches. Results show significant performance improvement in terms of total execution time of up to 370%, 408%, 477%, and 550% when using configurations developed based on genetic algorithm, forward, virtually inverse, and hybrid data exchange techniques, respectively.
Thesis (Ph. D.)--California Institute of Technology, 1980. Includes bibliographical references (leaves 181-185). Typescript (photocopy).
This paper presents analysis and synthesis techniques for multicomputer networks that perform fast reconfiguration into rings, stars, and trees. Each reconfiguration into a new network structure requires only two codes (reconfiguration code RC and bias B), and can be performed during one clock period. Because the reconfiguration methodology presented is based on some fine mathematical properties exhibited by special shift registers with variable bias (SRVB), they are also introduced in this paper.
A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy.
A generalized architecture is presented for reconfigurable m -ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with m k processing elements or nodes (where k is any integer >1) is implemented with a k -stage MIN. A single control code issued to the MIN establishes a distinct m -ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m -ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed
A novel approach to the design of a reconfigurable tree
architecture is presented. The architecture is implemented with an
augmented shuffle-exchange multistage interconnection network and is
capable of assuming N distinct binary tree configurations,
where N is the number of processing elements (PEs) in the
system. The novel features of the architecture include fast switching
from one configuration to another, simplified hardware in the PEs and
the switching network, and simple routing control
Reconfiguration strategies for parallel architectures
- Yellamanchili