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DDR3 SDRAM with a complete predictor
Abstract
In the arsenal of resources for improving computer memory system
performance, predictors have gained an increasing role in the past few
years. They enable hiding the latencies when accessing cache or main
memory. In our previous work we proposed a DDR SDRAM controller with
predictors that not only close the opened DRAM row but also predict the
next row to be opened. In this paper we explore the possibilities of
trying the same techniques on the latest type of DRAM memory, DDR3
SDRAM, with further improvements of the predictors.
In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They can suppress the latencies when accessing cache or main memory. In our previous work we proposed predictors that not only close the opened DRAM row but also predict the next row to be opened, hence the name 'Complete Predictor'. It requires less than 10 kB of SRAM for a 2GB SDRAM system. In this paper we evaluate how much additional hardware is needed and whether the activations of the predictors will slow down the DRAM controller. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.
Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM
device state. It is shown that execution time can be reduced by using a state machine which predicts, for each access, the
policy which will minimize latency. Two-level dynamic predictors are incorporated into the SDRAM controller. A range of organizations
for dynamic predictors are described, and the performance improvements predicted by simulation are compared using execution
time and prediction accuracy as metrics. Results show that predictive SDRAM controllers, reduce execution time by 1.6% to
17% over static access control policies. The prediction accuracy of the best predictor results in 93% prediction accuracy,
with 87% accuracy for OP state preferred accesses, and 96% for CPA state preferred accesses. Results show that execution time
is strongly correlated to the prediction accuracy of OP, suggesting directions for future predictor development.
In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper[1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.