added 2 research items
Approximate DRAMs are DRAM memories where energy saving techniques have been implemented by trading off bit-cell error rate with power consumption. They are considered part of the building blocks in the larger area of approximate computing. Relaxing refresh rate has been proposed as an interesting solution to achieve better efficiency at the expense of rising error rate. However, some works have demonstrated that much better results are achieved if at word-level some bits are retained without errors (i.e. their cells are refreshed at nominal rate), resulting in architectures using multiple refresh rates. In this paper we present a technique that can be applied to approximate DRAMs under reduced refresh rate. It allows to trim error rate at word-level, while still performing the refresh operation at the same rate for all cells. The number of bits that are protected is configurable and depends on output quality degradation that can be accepted by the application.
In this paper, an emulation environment for approximate memory architectures is presented. In the context of error tolerant applications, in which energy is saved at the expense of the occurrence of errors in data processing, approximate memories play a relevant part. Approximate memories are memories where read/write errors are allowed with controlled probability. In general these errors are the result of circuital or architectural techniques (i.e. voltage scaling, refresh rate reduction) introduced to save energy. The ability to simulate these systems is particularly important since the amount of tolerated error is application dependent. Simulation allows to analyze the behavior of an application and explore its tolerance to actual error rates, determining the trade-off between saved energy and output quality. We have developed an emulation environment for such architectures, based on QEmu, which allows the execution of programs that can allocate some of their data in a memory zone subject to faults. We present the emulated architecture, the fault injection model and a case of study showing results that can be obtained by our emulator.