Zongliang Huo

• Institute of Microelectronics, Chinese Academy of Sciences

Hafnium-based ferroelectric materials have attracted a lot of attention, but the distributions of the materials need to be tuned for commercialization, including phase distribution and polarization orientation distribution. The orientation of ferroelectric materials plays a significant role in memory device performance; however, there have been no...

Quad-level cell (QLC) has received significant attention recently due to its extremely high storage capacity. However, because of its poor reliability, QLC-based solid-state drives (SSDs) require a two-step programming to reduce the layer interference. But during the interval between two programming steps on the same wordline (WL), data could be in...

In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, wh...

To meet commercialization requirements, the distributions of materials in hafnium-based ferroelectric devices—including their phase and orientation—need to be controlled. This article presents a method for improving the ferroelectric phase ratio and orientation by adjusting the stress distribution of the annealing structure in a three-dimensional c...

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program’s performance cannot be...

3D NAND flash memory can be selected as a promising candidate for the implementation of neuromorphic computing ascribe to high density, low write power and multi-level storage capability. Nevertheless, the broader range of application domains, such as advanced deep learning training and linear and partial differential equations solving, require a h...

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate th...

We conducted a comprehensive investigation on the influence of TiN thickness and stress on the ferroelectric properties of Hf0.5Zr0.5O2 thin films. TiN top electrode layers with varying thicknesses of 2, 5, 10, 30, 50, 75, and 100 nm were deposited and analyzed. It was observed that the in-plane tensile stress in TiN films increased with the thickn...

Hf0.5Zr0.5O2 (HZO) is a promising candidate for low-power non-volatile memory due to its nanoscale ferroelectricity and compatibility with silicon-based technologies. Stress and oxygen vacancy (VO) are key factors that impact the ferroelectricity of HZO. However, their combined effects have not been extensively studied. In this study, we investigat...

Although NAND flash memory does a lot of work in effectively using Error Correcting Code(ECC) to reduce Uncorrectable Bit Error Rate(UBER). However, if the Frame Error Rate(FER) is not reduced, the lower UBER cannot effectively reduce the read latency of the flash memory system. This phenomenon is especially evident at the end of the flash memory l...

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced...

3D NAND flash memory constitutes strong competitors for neuromorphic computing due to its high density and mature technology. Neural networks based on 3D NAND flash differential pair have been reported since conventional block erase scheme hinders individual conductance modulation. However, the differential pair scheme halves the efficient synaptic...

The ferroelectric field effect transistor (FeFET) is a very promising candidate for low-power and non-volatile memory. However, the co-existing effect of ferroelectric polarization and interface charge trapping in the FeFETs is demonstrated and many efforts have been made to eliminate this charge-trapping effect, which is usually treated as a delet...

With the development of storage technology, NAND Flash’s reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC...

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. T...

3D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity1. However, the 3D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is diff...

Self-organizing Map (SOM) neural network is a prominent algorithm in unsupervised machine learning, which is widely used for data clustering, high-dimensional visualization, and feature extraction. However, the hardware implementation of SOM is limited by the von Neumann bottleneck. Herein, a SOM neural network is implemented by the combination of...

As the storage density of 3D NAND flash memory increases, reliability issues become a bottleneck. Among all reliability issues, decreased retention time is the dominant one. To extend the retention time, data refresh is a straightforward approach. However, refresh operations introduce redundant operations, which hurt the performance of the 3D NAND...

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to...

Read retry technique intended to reduce read errors by searching the optimal read voltages and the low density parity check (LDPC) code aimed to correct the reduced read errors are widely used in storage systems to improve reliability of the 3D NAND flash memories. However, the read retry operation and LDPC decoding operation generate long read lat...

The dual-deck architecture with aligned upper and lower decks is considered a promising technology to meet the demand of increasing word-line (WL) layers of 3D NAND flash. However, the relevant reliability studies are still lacking for the dual-deck 3D NAND array. In this work, it is reported an abnormal program disturbance phenomena of the bottom...

As an important constraint on the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) distribution, the random telegraph noise (RTN) has attracted much attention due to the widely used multi-bit-per-cell technology in 3D NAND flash. This work investigated the physical mechani...

The detection of temporal correlations among event-driven data streams is widely demanded in data-intensive applications such as edge computing. In this work, temporal correlation detection is enabled by the combination of 3D NAND flash and in-memory computing. Different from mathematical scheme by covariance matrix calculation, here the detection...

Voltage controlled magnetic anisotropy (VCMA) has been considered as an effective method in traditional magnetic devices with lower power consumption. In this article, we have investigated the dual-axis control of magnetic anisotropy in Co2MnSi/GaAs/PZT hybrid heterostructures through piezo-voltage-induced strain using longitudinal magneto-optical...

The non-volatility of NAND flash memory is guaranteed only when data errors are within the ECC correction capability. With data errors exceeding ECC correction capability due to the retention process, the data recovery technique is a straightforward way to reduce retention errors to be correctable by ECC. In this paper, a high-efficient data recove...

Valley search aims to find the updated optimal read reference voltage (OPT) that minimizes the raw bit error rate (RBER). In this paper, a valley search algorithm is proposed, which can accurately find the OPT after five read operations through a simple calculation based on cubic polynomial approximation, without traversing all the read voltages be...

Experimental demonstration of unsupervised learning is realized with charge-trapping 3D NAND flash device array. The charge-trapping characteristic of the memory cell is leveraged so that the devices perform not only as non-volatile memory but also synaptic cells in hardware neural network. Experiments reveal that the 3D NAND flash devices hold goo...

Experimental results indicate that the conventional program suspend scheme in 3D NAND flash memory chip can generate unexpected additional read fail bits and reduce the reliability of 3D NAND flash memory. These extra read fail bits are observed when the program suspend command is issued during the program stage, and particularly, they become more...

TLC NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase of the storage density, lower reliability results in more read times for flash memory and significantly reduces read performance. In order to avoid unnecessary read operations, this paper proposes a hard decision-soft decoding metho...

The high thermal budget of three-dimensional NAND Flash (3D NAND Flash) is the key issue limiting the increase in vertical integration. The main purpose of this article is to design a local and high temperature annealing function to reduce the thermal budget and gain a high activation rate without diffusion at a target depth to improve the performa...

In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAN...

In the 3D NAND Flash memory manufacturing process, high-concentration in-situ phosphorus-doped polysilicon and TEOS oxide stack will produce bump defects at the interfaces, causing pattern defects and electrical failures. The formation mechanism of bump defects caused by oxygen-containing groups and phosphorus at the lower and upper interfaces of p...

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of thres...

The magneto-electric coupling (MEC) effect has been considered an effective method for the voltages controlled magnetic anisotropy in traditional ferroelectric/ferromagnetic structures. Unlike traditional perovskite ferroelectrics, the ferroelectric hafnium-based oxides hold great potential for use in the complementary metal oxide semiconductors (C...

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND flash 1-4, and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress 81% of IVS...

Temporary read errors (TRE) refers to the high temporary fail bit count (FBC) in the first read, when 3D NAND recovers from an idle state 1. This can seriously deteriorate the Quality of Service (QoS) of 3D NAND Flash-based storage devices. The characteristics and mechanism of the TRE issue of 3D NAND Flash are investigated in this work. Based on t...

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock...

3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, howev...

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (O1) layer...

It is difficult to adjust asymmetrically saddle-shape wafer warpage resulted from high-stress material in 3D NAND Flash memory. This paper proposes a novel method that the suitable trenches on the backside of wafer is formed to improve saddle-shape warpage asymmetrically. Effects of different trench pitches, CDs and depths are studied by FEM (finit...

Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH et...

The impact of linear correlation between lognormal distribution grain size mean and sigma along the polysilicon channel on threshold voltage (Vth) variability has been investigated in three dimensional (3D) NAND flash. The variety of grain size mean and sigma results in the unstable Vth variability. To obtain a stable Vth distribution with various...

As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (ve...

The mechanisms and characteristics of program noise (PN) in charge trap based 3D NAND flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible for PN. Moreover, it is found that PN gets worse after program and erase (PE) cycling in 3D charge trapping memory devices. A physical model is proposed...

We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Bas...

Cu diffusion caused by stress, current or light induced migration in Cu interconnect is the main cause of circuit failure in BEOL (Back End of Line) process. The diffusion at the Cu/cap layer interface has been widely demonstrated to be the main path of copper diffusion. The copper diffusion between the copper line and the upper cap layer is studie...

An effective post etch treatment (PET) process was proposed to eliminate etch damage in the channel hole, of which the depth and the aspect ratio is beyond 3 μm and 30:1 respectively, prior to selective epitaxial growth (SEG) in three dimensions (3D) NAND flash memory. In this work, it is demonstrated that the damaged layer both at the channel hole...

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and impr...

In this study, the wafer warpage resulting from common source line tungsten (CSL W) is investigated in 3D NAND flash memory. It is found that the warpage is related to the annealing conditions after CSL W deposition, and it reduces exponentially with increasing annealing temperature or linearly with increasing annealing time. This result shows that...

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different t...

The electrical characteristics of top select gate transistor (TSG) has been investigated in vertical channel three dimensional NAND flash memory. TSG shows wider initial Vth distribution as compared with memory cells, and even worse after erase. By experimental analysis and TCAD simulation, a physical model based on grain boundary (GB) interface tr...

Erase cycling induced Vt shift of top select gate transistor (TSG) and its physical mechanism are studied in 3D NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells erase cycling. Furthermore, the TSG Vt shift can recover after the removal of cycling stress. A physical model of trap generation induced by...

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as conventio...

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-ty...

The disturbance mechanism of dummy cell during memory cell cycling has been investigated in 3D NAND flash. Edge dummy cell (DMY) threshold voltage (Vt) increasing was observed during cell program and erase cycling, which leads to a reduced string current and read failure. According to experiment and TCAD analysis, two mechanisms were identified to...

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. B...

A new read scheme is proposed to suppress read disturbance in unselected strings of three dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppr...

This paper represents a 4.5V regulated charge pump with extremely small ripple. The pump designed with Voltage Doubler (VD) significantly reduces the output ripple voltage. In addition, this circuit utilizes a controllable pumping current (CPC) technology, which achieves automatically adjusting output current by feedback mechanism and resizing tran...

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been propose...

To meet the storage requirement of big data, charge trap concept-based three dimensional charge trapping memory (3D-CTM) becomes the main trend of flash technology development. With the multi-layer gate stacking, the equivalent technology node can be scaled down to 10nm without the serious reliability problems from cell-to-cell coupling and SILC-in...

With conventional nonvolatile flash memories approaching their scaling limit from cell-to-cell coupling and stress induced leakage current, many studies have been performed to explore the next generation memory technologies. Metal floating gate (FG) memory is one of the most promising candidates because of its less ballistic transport even with ultr...

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2X nm. In this work, metal FG memory device with high-k engineered Inter-Gate-Dielectric (IGD) and/or tunneling layer (TL) was detailed investigated. It presents improved performance wi...

A novel adaptive CMOS low-dropout regulator (LDO) is proposed for DDR4 memory power supply. By using a two stage structure, this LDO can adjust its transfer path to afford a very large range of load current from 0 A to 3 A. Two NMOS pass elements are used to do both sourcing and sinking functions, which are not included in traditional LDOs. The imp...

This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus...

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models o...

The dependence of complex random telegraph noise (RTN) behavior on gate bias is investigated. Noise-type transition among 1/f noise, two-level RTN, and three-level RTN is observed depending on the gate bias. The transition can be detected in both program and erase states and the corresponding transition voltage decreases with the increase of thresh...

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep sub-micron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estim...

Volatile threshold switching (TS) and non-volatile memory switching (MS) are two typical resistive switching (RS) phenomena in oxides, which could form the basis for memory, analog circuits, and neuromorphic applications. Interestingly, TS and MS can be coexistent and converted in a single device under the suitable external excitation. However, the...

The retention characteristics of electrons and holes in hafnium oxide with post-deposition annealing in a N2 or O2 ambient were investigated by Kelvin probe force microscopy. The KFM results show that compared with the N2 PDA process, the O2 PDA process can lead to a significant retention improvement. Vertical charge leakage and lateral charge spre...

We report that by heating samples the critical current density for magnetization reversal (Jc) in a single perpendicularly magnetized layer can be decreased from 2.6 × 107 A/cm2 to about 1 × 106 A/cm2 for a temperature increase of 143 K. The nonlinear dependence of Jc on the perpendicular anisotropy field indicates that the coherent magnetic switch...

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of nand flash technology node beyond (2times ) nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO2/HfO2 dual-layer engineered tunneling barrier shows good memory characteristics. It presents...

The impact of program/erase (P/E) cycling on drain disturb in 65 nm-node NOR flash memories is studied. It is shown that the drain disturb is originated from the hot-hole-injection (HHI) induced by band-to-band tunneling (BBT) when programming operation. The drain disturb becomes more severe as cycles increase due to the negative traps and interfac...

The effect of pre-annealing to blocking oxide on the performance of trapping layer engineered charge trapping flash memory was investigated in this work. Compared to the devices fabricated by conventional process, the devices with pre-annealing treatment exhibit larger memory window, faster program speed, and significantly improved data retention....

Uniformity issue and data retention are two severe challenges for resistive random access memory (RRAM). The wide dispersion of high resistance state (HRS) is the main cause of uniformity issue. In this work, a novel programming scheme named gate induced resistive switching is proposed to improve the reliability of RRAM in one transistor and one re...

The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a...

The impact of key process parameters on the electrical characteristics of atomic layer deposited HfO2 films has been systematically studied with MHOS devices via capacitance–voltage (C–V) measurement. C–V hysteresis curves revealed that charge storage capacity is significantly enhanced with decreasing substrate temperature from 350 down to 150 °C a...

This paper presents an embedded SRAM design for write buffer applications in flash memories. The write buffer is implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6 T SRAM cell units. A 2 kb SRAM macro with the area of 135 μm × 180 μm is implemented in and applied to a 128 Mb NOR flash me...

On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel ov...

Charge-trapping memory with high-κ insulator films is a candidate for future memory devices. Many efforts with different indirect methods have been made to confirm the trapping position of the charges, but the reported results in the literatures are contrary, from the bottom to the top of the trapping layers. Here we characterize the local charge d...

One time programming memory and methods of storage and manufacture of the same are provided. Examples relate to microelectronic memory technology and manufacture. The one time programming memory includes a diode (10) having a unidirectional conducting rectification characteristic and a variable-resistance memory (20) having a bipolar conversion cha...

In this letter, the retention properties of charge trapping memory with decreased thickness of ultra-thin HfO2 charge trapping layer are investigated by Kelvin probe force microscopy (KFM) technology. Experiment results show that retention properties became worse with the reducing of HfO2 thickness and increasing of temperature. Based on total rema...

Graphene exhibits unique electronic properties, and its low dimensionality, structural robustness, and high work-function make it very promising as the charge storage media for memory applications. Along with the development of miniaturized and scaled up devices, nanostructured graphene emerges as an ideal material candidate. Here we proposed a nov...

Supplementary Information

The effects of interfacial fluorination on the metal/Al2O3/HfO2/SiO2/Si (MAHOS) memory structure have been investigated. By comparing MAHOS memories with and without interfacial fluorination, it was identified that the deterioration of the performance and reliability of MAHOS memories is mainly due to the formation of an interfacial layer that gene...

In this letter, the retention properties of charge trapping memory with decreased thickness of ultra-thin HfO 2 charge trapping layer are investigated by Kelvin probe force microscopy (KFM) technology. Experiment results show that retention properties became worse with the reducing of HfO 2 thickness and increasing of temperature. Based on total re...