Yeoul Na

University of California, Irvine | UCI · Department of Computer Science

N-Variant Execution (NVX) systems utilize artificial diversity techniques to enhance software security. The general idea is to run multiple different variants of the same program alongside each other while monitoring their diverging behavior on a malicious input. Existing NVX systems execute diversified program variants on a single host. This means...

N-Variant Execution (NVX) systems utilize software diversity techniques for enhancing software security. The general idea is to run multiple different variants of the same program alongside each other while monitoring their run-time behavior. If the internal disparity between the running variants causes observable differences in response to malicio...

Compile-time specialization and feature pruning through static binary rewriting have been proposed repeatedly as techniques for reducing the attack surface of large programs, and for minimizing the trusted computing base. We propose a new approach to attack surface reduction: dynamic binary lifting and recompilation. We present BinRec, a binary rec...

Data-oriented attacks are gaining traction thanks to advances in code-centric mitigation techniques for memory corruption vulnerabilities. Previous work on mitigating data-oriented attacks includes Data Space Randomization (DSR). DSR classifies program variables into a set of equivalence classes, and encrypts variables with a key randomly chosen fo...

The C and C++ programming languages are notoriously insecure yet remain indispensable. Developers therefore resort to a multi-pronged approach to find security issues before adversaries. These include manual, static, and dynamic program analysis. Dynamic bug finding tools --- henceforth "sanitizers" --- can find bugs that elude other types of analy...

In the continuous arms race between attackers and defenders, various attack vectors against script engines have been exploited and subsequently secured. This paper explores a new attack vector that has not received much academic scrutiny: bytecode and its lookup tables. Based on our study of the internals of modern bytecode interpreters, we present...

A memory controller refreshes DRAM rows periodically in order to prevent DRAM cells from losing data over time. Refreshes consume a large amount of energy, and the problem becomes worse with the future larger DRAM capacity. Previously proposed selective refreshing techniques are either conservative in exploiting the opportunity or expensive in term...

With the advent of the HTML5 standard, JavaScript is increasingly processing computationally intensive, data-parallel workloads. Thus, the enhancement of JavaScript performance has been emphasized because the performance gap between JavaScript and native applications is still substantial. Despite this urgency, conventional JavaScript compilers do n...

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special...

Recently, the internet of things (IoT) has become increasingly attractive in many areas to realize smart worlds. JavaScript has become prevalent for IoT programming because of its familiarity with web programmers. On the other hand, JavaScript does not allow the direct control of IoT hardware due to its language limitation. This paper proposes the...

The GCC2Verilog compiler, a fully automatic HLL-to-HDL translator as the GCC Verilog backend, supports all the features of C and C++ languages. However, there is still a large performance gap between the hand-optimized and the GCC2Verilog generated hardware. This paper shows the quantitative performance gap in the Viterbi decoder implementation as...

Many GPUs have become available in a consumer electronics market due to their performance and power efficiency. However, the internal implementations of GPU compilers are still undisclosed to our community. In this paper, we show implementation of a frontend compiler for OpenGL ES Shading Language on GPUs, which is based on the LLVM compiler. We ve...

A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following...

Recently PDP market has been shrinking gradually, but the expansion of 3D (3 dimensional) TV provides a new opportunity to PDP of retrieving its market share by favor of its higher response speed over LCD. In this paper, we propose a novel processor-based decoupled PDP timing controller design which is flexible, and therefore meets the design requi...

This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.

In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our pr...