Xiaobin He

• Chinese Academy of Sciences

Location-controlled single grains were obtai-ned through amorphous silicon grown on substrates embedded with microstructure called grain filters (GFs) using long-pulse green laser annealing. This work demonstrates the significant influence of GF spacing and size on grain quality. Accomplished results in this work evidenced that defects like grain b...

Experimental results of controlled Fano lineshapes in coupled nanobeam cavity-waveguide structure by tuning the defect waveguide are reported. The devices are fabricated on a standard full-process CMOS passive multi-project-wafer run with 180 nm technology node. This work provides potential for advanced and scalable integrated photonics application...

Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed and experimentally fabricated. The growth of bottom SiGe layer with different Ge fraction following by an accurately selective etching is developed for realizing SiGe nano-fins...

Advanced silicon photonic technologies enable integrated optical sensing and communication (IOSAC) in real time for the emerging application requirements of simultaneous sensing and communication for next-generation networks. Here, we propose and demonstrate the IOSAC system on the silicon nitride (SiN) photonics platform. The IOSAC devices based o...

This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dime...

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching prope...

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the correspondin...

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si s...

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the origi...

We experimentally investigate the effect of post-deposition annealing on the charge distribution of a metal-oxide-semiconductor capacitor with a TiN/HfO2/SiO2/Si gate structure. We decoupled interfacial charges at the SiO2/Si and HfO2/SiO2 interfaces; bulk charges in HfO2; and the dipole formation at the HfO2/SiO2 interface. The interfacial charges...

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) al...

In this work, a novel method consisting of side-wall passivation and a top-metal reveal process is proposed for spintronics devices based on magnetic tunnel junctions (MTJs). The method can efficiently protect ferromagnetic metals and magnesium oxide, which are the key materials of MTJs, and effectively establish electrical contact with the interco...

Perpendicular magnetic tunnel junction (p-MTJ) provides advantages such as infinite endurance, high thermal stability, fast and low-power switching. It is considered as a promising non-volatile memory device to build non-von Neumann computing paradigms and definitively overcome the power bottleneck. Numerous design proposals have been made for p-MT...

Metal structures with taper angles and smooth sidewalls are very useful in theoretical analyses. In this study, an approach for implementing this kind of metal structure is developed, and an analytical model is discussed in detail. Using this method, an experimental investigation on plasma etching of Mo is conducted. By optimizing the process param...

A novel nanofabrication technique which can produce highly controlled silicon-based nanostructures in wafer scale has been proposed using a simple amorphous silicon (α-Si) material as an etch mask. SiO2 nanostructures directly fabricated can serve as nanotemplates to transfer into the underlying substrates such as silicon, germanium, transistor gat...

We propose a novel CMOS-compatible top-down nanofabrication technique of highly-ordered Si-based nanostructures using a single amorphous silicon (α-Si) material. The pattern of α-Si layer is precisely transferred into the underlying SiO 2 material. Then, various well-controlled SiO 2 nanostructures fabricated by this approach can be used as nanotem...

As continue shrinking of microelectronic device features, removal of nano-particle contaminations is becoming a major challenge in semiconductor manufacturing. After effective wafer cleaning, high particles removal efficiency must be achieved without substrate loss or damage to high aspect ratio structures. In this work, a novel dual-fluid spray no...

We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO 2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO 2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used...

In this work, we investigated the challenges encountered in 14 nm node Finfet gate patterning. The patterning process was originated from a 22 nm planar device, in which a SiO2/Si3N4/SiO2 (ONO) multilayer was used as an etch mask. To accommodate with the 3D nature of Finfet structures in 14 nm node, the thickness of Si3N4 has been increased in the...

In this work, we have demonstrated a straightforward and CMOS-compatible nanofabrication technique that can produce well-ordered periodic SiO2 nanohole arrays in wafer-scale using a single amorphous silicon (α-Si) layer. It is the first time that α-Si material has been used as an etch mask to fabricate SiO2 nanostructures. Our results have shown th...

As an emerging lithographical technique, DSA has drawn increasingly attentions due to numerous advantages such as low cost, high throughput and convenience on processing. However, there are still some challenges confronted with DSA, including defects control, complex patterns fabrication and pattern registration. In this work, self-assembling morph...

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical va...

In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the polysilicon gate etch based on the composite SiO2/Si3N4/SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferre...

The 3D tri-gate FinFET device architecture is a key transistor scaling to 22nm node and beyond for its excellent short-channel performance[1]. However, compared with planar transistors, it poses greater challenge in the finFET gate etch.[2] As shown in fig.1, the etch needs to stop on top of the fin while etching further down to the STI oxide layer...

FinFETs with 20nm BEOL with one generation improvement in performance and power efficiency has announced for mass production by leading IC companies. The processing details, however, have never been reported. In this talk, processing challenges of CMOS integration of FinFETs with all-last gate stacks is presented based on our recent results. Specia...

In this work, we have investigated the evolution of line roughness from e-beam lithography to final gate patterning based on conventional SiO2/Si3N4/SiO2 (ONO) hard mask using a Capacitively Coupled Plasma (CCP) etcher. A severe roughness was observed on gate patterning line when PR patterns were directly transferred into ONO hard mask even if a hi...

In this work, PVD and ALD TaN were evaluated as wet etch stop layer (WESL) in order to selectively remove TiN & Ti in the high-k/metal gate (HKMG) gate last CMOS integrations. The selectivity of TiN & Ti towards PVD or ALD TaN is achieved at least 5.6 with an ammonia hydrogen peroxide mixture (APM). In case of PVD TaN, nitrogen content in the film...

HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET...