Wei Zuo

Wei Zuo
University of Illinois, Urbana-Champaign | UIUC · Department of Electrical and Computer Engineering

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12
Publications
4,012
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249
Citations

Publications

Publications (12)
Conference Paper
Full-text available
FPGAs have been rapidly adopted for acceleration of Deep Neural Networks (DNNs) with improved latency and energy efficiency compared to CPU and GPU-based implementations. High-level synthesis (HLS) is an effective design flow for DNNs due to improved productivity, debugging, and design space exploration ability. However, optimizing large neural net...
Conference Paper
Full-text available
FPGAs have been rapidly adopted for acceleration of Deep Neural Networks (DNNs) with improved latency and energy efficiency compared to CPU and GPU-based implementations. High-level synthesis (HLS) is an effective design flow for DNNs due to improved productivity, debugging, and design space exploration ability. However, optimizing large neural net...
Conference Paper
A desirable feature of a development tool for SoC design is that, given the important applications in the domain to be targeted by the SoC, a powerful hardware-software partitioning engine is available to determine which function(s) shall be mapped to hardware. However, to provide high-quality partitioning, this engine must be able to consider a ri...
Chapter
Full-text available
The rise of the Internet of Things—billions of internet connected sensors constantly monitoring the physical environment has coincided with the rise of big data and advanced data analytics that can effectively gather, analyze, generate insights about the data, and perform decision making. Data analytics allows analysis and optimization of massive d...
Conference Paper
While SystemC models provide a promising solution to the complex problem of HW/SW co-design within the system-on-chip paradigm, such requires a detailed annotation of transaction level energy and performance data within the model. While this data can be obtained through source code profiling of an application running on the target processor, accomp...
Article
The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniq...
Conference Paper
Full-text available
Analysts estimate that there will be 50 billion internet-connected devices by 2020, from 25 billion in 2015. This predicted explosion of IoT devices affects various evolving and growing markets as well as entirely new applications. Despite the variety of target applications, all such devices demand low energy/power consumption, high reliability, co...
Conference Paper
Full-text available
Due to the continually growing complexity demands of integrated circuits (ICs), electronic design automation flows must enable efficient design of ICs through design entry at higher abstraction levels. IC design has gradually transitioned from circuit-level to logic-level, register-transfer level, behavioral-level and now electronic-system-level de...
Conference Paper
High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with th...
Conference Paper
Full-text available
High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimiza...

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