Vladimir Stankovic

University of Niš | NIS · Department of Computer Science

In modern computing technique, calculation of leading zeros in a data represented as strings of digits is used very often. Those techniques require high speed of the circuit, as well as its fast design. In this paper we propose a design of such a counter, which is applicable to data length of w = 4j bits, for 4 < j ≤ 8. With this solution it is als...

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress latencies when accessing cache or main memory. In our previous work we considered using predictors to decrease Synchronized Dynamic Random Access Memory (SDRAM) latency. If one wants to apply...

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They can suppress the latencies when accessing cache or main memory. In our previous work we proposed predictors that not only close the opened DRAM row but also predict the next row to be opened, hence the...

In the last several decades there has been a revolution going on in the self-development area. Every day it becomes more and more clear that one of the main things influencing the quality of people's lives is their way of thinking. One's mental attitude influences not only their mental aspects like self-esteem and confidence but it outspreads to li...

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next...

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper[1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used fo...

Better insight of programs behavior can help in overcoming large speed difference of central processors and main memories implemented with DRAM chips. It allows us to predict required next actions, based on observed main memory access patterns, which can hide some time components in accessing DRAM memory. Authors of this paper proposed a simple dea...

In the arsenal of solutions for computer memory system performance improvement, predictors have gained an increasing role in the past years. They enable hiding the latencies when accessing cache or main memory. Recently the technique of using temporal parameters of cache memory accesses and tag patterns observing has been applied by some authors fo...

Performances of DRAM memories are characterized by memory latency and bandwidth. Contemporary DRAM memories more successfully satisfy demands for higher bandwidth than lower latency. In this paper solutions, which may reduce latency of these memories, are investigated. These solutions are two new controller policies called 'Write-miss Only Close-Pa...

DRAM memory performance is critical, factor in many multimedia applications. Some techniques, which improve DRAM memory performance, are proposed in this paper. These are, first, combined strategies of opening and closing DRAM pages, and second, address remapping in DRAM memory referencing. Simulations we have done showed some improvements in laten...

DSP and multimedia applications can be very demanding of memory parameters. Typical requirements of memory parameters in such applications are quoted in the paper. Based on these requirements, two types of contemporary DRAM memories, Rambus DRAM and SLDRAM, are considered as candidate memories in such systems. The results given in the paper show th...

Sadržaj – Pristupi dinamičkoj (SDRAM) memoriji uključuju tri aktivnosti: pretpunjenje, aktiviranje (Abstract – Dynamic memory accesses include three activities: precharge, row activation and column access, each of about 15 ns or more. For a sequence of successive accesses to columns into the same row of a bank, precharge and row activation must pre...