Vincenzo Della Marca

Aix-Marseille University | AMU · Institut Matériaux Microélectronique et Nanosciences de Provence (UMR 7334 IM2NP)

Dans le cadre du Cycle Ingénieurs de la Filière « Microélectronique et Télécommunications » de Polytech Marseille, différents enseignements sont directement articulés autour du procédé MOS proposé dans la salle blanche de l’Atelier Interuniversitaire de Micro-Nano Électronique (AIME, Pôle CNFM de Toulouse). En effet, les TP de physique des composan...

This work addresses the reliability of different architectures of novel high-density multi-gate transistors manufactured in a 40 nm embedded non-volatile memory process technology. The multi-gate architectures are based on lateral transistors integrated in deep trenches built alongside the main planar transistor. These architectures increase the co...

Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and t...

Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and t...

In this paper we present an experimental study on the preswitching time of Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) with a resistance area R.A. ~ 12 Ω.μm², for both transitions, Anti-Parallel to Parallel state and vice versa. A set of measurements is carried out operating at different applied voltages and temperatures ranging f...

In this paper a new experimental technique for measuring the switching dynamics and extracting the energy consumption of Spin Transfer Torque MRAM (STT-MRAM) device is presented. This technique is performed by a real-time current reading while a pulsed bias is applied. The switching from a high resistive state, anti-parallel (AP) alignment, to a lo...

This paper addresses the reliability on a novel trench-based Triple Gate Transistor (TGT) fabricated in a 40 nm embedded Non-Volatile Memory (e-NVM) technology. In the studied device, two vertical transistors are integrated in deep trenches alongside the main planar transistor to build a TGT. The reliability of this device is investigated targeting...

In this paper, we present an experimental study of a new architecture of the embedded Select in Trench Memory (eSTM™) cell. A first part is dedicated to a deep analysis of the overlap eSTM™ behaviour. A key fact is the possibility to achieve a large programming window thanks to tip effect enhanced erase. After the study on erase operation scheme, w...

This paper addresses the design, implementation, and characterization of a novel high-density Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing proce...

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapour, 4-7 Oct. 2021

This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in...

A novel True Random Number Generator circuit fabricated in a 130 nm HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the prop...

The behaviour of semiconductor materials and devices subjected to femtosecond laser irradiation has been under scrutiny, for many reasons, during the last decade. In particular, recent works have shown that the specific functionality and/or geometry of semiconductor devices, among which non-volatile memory (NVM) devices hold a special place, could...

We perform experiments and device simulations to investigate the origin of current–voltage ( I–V ) linearity of TaO <sub xmlns:xlink="http://www.w3.org/1999/xlink"> x </sub> -based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the elect...

Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40 nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Elec...

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters ar...

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturall...

In this paper the impact of the endurance degradation on the programming window and the energy consumption of Flash floating gate memories is investigated. We use TCAD simulations to confirm, predict and explain the behavior we have observed in previous experimental studies. These simulations have been developed for 90nm technology node Flash float...

The interaction of ultrashort infrared laser pulses with bulk silicon is known to produce high electron density (~10^19 cm^-3) [1] induced by two-photon absorption mechanism [2]. Moreover, a recent theoretical study shows the impossibility to damage the material in the femtosecond regime [3]. All these benefits make embedded nonvolatile flash memor...

The interaction of ultrashort infrared laser with bulk silicon is known to produce high free-carrier densities. This regime is thus attractive for contactless reliability tests inside silicon embedded technologies. We detail a method to inject free-carriers by backside irradiation of silicon-supported transistor structures and report on the tunneli...

In this paper we present the behavior of a single nonvolatile Flash floating gate memory cell when it is irradiated, from the backside, by femtosecond laser pulses. For the first time we show that the memory cell state can change using this type of stimulation. The measurements were carried out with an experimental setup with an ad hoc probe statio...

The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we pro...

This chapter presents an overview of the charge trap, silicon nanocrystals and split-gate memory technologies, which are currently envisaged as promising solutions to solve the scaling issues of standard embedded Flash memory technologies. In particular, we will focus on the main features allowing improved performance and scaling perspectives. We w...

In this paper we propose to modify the pulses classically used during the channel-hot-electron programming phase of a Flash memory and to replace it by a sequence of ultra-short pulses in order to decrease the programming window closure observed during the endurance test. We start this work presenting the other solutions published in literature. Th...

In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming oper...

In this paper the impact of the endurance degradation on the programming window and the energy consumption of flash floating gate memories is investigated. Using a new measurement technique we characterized the evolution of the dynamic drain current during the channel hot electron programming through the cycling. This experimental method has been d...

In this paper, the electrical instabilities of Inter Metal Dielectric (IMD) SiOCH are investigated. These instabilities concern leakage current between metal lines and dielectric breakdown. At room temperature IMD leakage current tends to increase with waiting time. At high temperature and without electrical stress, a defect recovering phenomenon o...

The silicon nanocrystal memories are one of the most attractive solutions to replace the Flash floating gate for nonvolatile memory embedded applications, especially for their high compatibility with CMOS process and the lower manufacturing cost. Moreover, the nanocrystal size guarantees a weak device-to-device coupling in an array configuration an...

In this paper we present the last improvement on programming window and consumption of silicon nanocrystal memory cell (Si-nc). Using a dynamic technique to measure the drain current during the hot carrier injection (HCI) programming operation, we explain the behavior of Flash floating gate (F.G.) and silicon nanocrystal memories. We use TCAD simul...

The microelectronic industry requires more and more low consumption and high reliability solutions. In this scenario the silicon nanocrystal memories (Si-nc) are one of the most mature technologies able to replace the Flash floating gate in NOR embedded applications. The main advantages of Si-nc memories are: the full compatibility with the CMOS pr...

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current abso...

In this paper, we investigate the effects of variation of two process parameters, Lightly Doped Drain (LDD) implantation energy and Channel Doping Dose (CDD) variations, on Flash memory performances (programming efficiency, consumption energy). The reliability aspect is taken into account with endurance experiments to evaluate the impact of these p...

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area cov...

In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons...

In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows...

In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si3N4) and hybrid Sinc/SiN based split-gate memories, with SiO2 or Al2O3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-g...

The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating g...

In this paper we investigate the energy consumption of Discrete-Trap Silicon Nanocrystal (Si-nc) Nonvolatile Memory Cell during Channel Hot Electron programming operation. We compare this cell with a Floating Gate Flash in order to evaluate the current absorption and the energy consumption under different conditions. Using a commercial TCAD simulat...

We investigate the electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. For this purpose, we perform simulations using a physical model that reproduces the charge injection/trapping in TANOS devices, which is extended in order to...

Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges. Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Dependi...

In this paper we report results on PCM endurance failure characterization. We show that endurance failure is related to SET pulse features and we analyze and model SET operation to obtain a better understanding and improve endurance performance. Results give interesting insights on the crystallization process of GST material. SET obeys to a constan...

The systematic investigation of the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations is reported for the first time. We determined a dominance of electrons back-tunneling in the first part of the transient, and dominance of holes in the second par...

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperat...

Alumina is a key material for developing innovative Charge-Trapping Non-Volatile Memory (CT-NVM) devices. Al2O3 is used to implement the top dielectric in TANOS devices, and it has been proposed as trapping layer and to engineer the tunnel dielectric. Despite the large use of this material, the quantitative investigation of defect features still la...

We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET...