Vijay Iyengar

IBM · Business Analytics and Mathematical Sciences (BAMS)

We describe a methodology for identifying and ranking candidate audit targets from a database of prescription drug claims. The relevant audit targets may include various entities such as prescribers, patients and pharmacies, who exhibit certain statistical behavior indicative of potential fraud and abuse over the prescription claims during a specif...

We report the experience of implementing event detection analytics to monitor and forewarn oil production failures in modern, digitized oil fields. Modern oil fields are equipped with thousands of sensors and gauges to measure various physical and chemical characteristics of oil and gas from underground reservoirs to distribution systems. Data from...

Travel and Entertainment (T&E) expenses are under increasing scrutiny as one of the largest controlla ble indirect expenses in a firm. This involves internal audits and analysis by business controls personnel to iden tify fraud and misuse and to take appropriate corrective actions. We have developed a set of statistical mod els to identify suspicio...

The management of IT portfolios in most enterprises is a complex and challenging ongoing process. IT portfolios typically contain large numbers of inter-related elements. In this paper, we present a model and a method for determining and evaluating IT portfolio options for use as a decision aid in the ongoing management of the portfolio. Business b...

Detection of space-time clusters plays an important role in epidemiology and public health. Different approaches for detecting space-time clusters have been proposed and implemented. Many of these approaches are based on the spatial scan statistic formulation. One key aspect of these cluster detection methods is the choice of cluster shape. In this...

Detection of space-time clusters is an important function in various domains (e.g., epidemiology and public health). The pioneering work on the spatial scan statistic is often used as the basis to detect and evaluate such clusters. State-of-the-art systems based on this approach detect clusters with restrictive shapes that cannot model growth and s...

Health activity monitoring (HAM) has received increasing attention due to the rapid advances of both hardware and software technologies and strong environmental and public health needs. In this paper, we describe the architecture and implementation of the Epi-SPIRE prototype, which is a novel health activity monitoring system that generates alerts...

The usual block oriented timing analysis for logic circuits does not take into account functional relations between signals. If we take functional relations into consideration we may find that a long path is never activated. This observation can be used to calculate improved and more accurate delays. It is not practical to consider the complete tru...

Data on individuals and entities are being collected widely. These data can contain information that explicitly identifies the individual (e.g., social security number). Data can also contain other kinds of personal information (e.g., date of birth, zip code, gender) that are potentially identifying when linked with other available data sets. Data...

Recommender systems use historical data on user preferences and other available data on users (for example, demographics) and items (for example, taxonomy) to predict items a new user might like. Applications of these methods include recommending items for purchase and personalizing the browsing experience on a web-site. Collaborative filtering met...

Recommender systems use historical data on user preferences and other available data on users (for example, demographics) and items (for example, taxonomy) to predict items a new user might like. Applications of these methods include recommending items for purchase and personalizing the browsing experience on a web-site. Collaborative filtering met...

Recommender systems use historical data on user preferences and other available data on users (e.g., demographics) and items (e.g., taxonomy) to predict items a new user might like. Applications of these methods include recommending items for purchase and personalizing the browsing experience on a web-site. Collaborative filtering methods have focu...

Forestry management requires careful and intensive planning efforts to ensure optimal yield, ecological stability, and regulatory compliance. In this paper, we describe a method of identifying wetlands and producing maps of their extent from commonly available, remotely-sensed imagery. This method provides a large labor savings over both field insp...

Forestry management requires careful and intensive planning efforts to ensure optimal yield, ecological stability, and regulatory compliance. We describe a method of identifying wetlands and producing maps of their extent from commonly available, remotely-sensed imagery. This method provides a large labor savings over both field inspections and man...

The task of evaluating and ranking items with multiple-attributes appears in many guises in commerce. Examples include evaluating responses to a request for quotes (RFQ) for some item and comparison shopping for an item within one or more catalogs. This task is straightforward if the value of the item can be explicitly specified by the evaluator as...

Classification modeling (a.k.a. supervised learning) is an extremely useful analytical technique for developing predictive and forecasting applications. The explosive growth in data warehousing and internet usage has made large amounts of data potentially available for developing classification models. For example, natural language text is widely a...

This paper presents a new method (HOT) of generating oblique decision trees. Oblique trees have been shown to be useful tools for classification in some problem domains, producing accurate and intuitive solutions. The method can be incorporated into a variety of existing decision tree tools and the paper illustrates this with two very distinct tree...

Performance evaluation of processor designs using dynamic instruction traces is a critical part of the iterative design process. The widening gap between the billions of instructions in such traces for benchmark programs and the throughput of timers performing the analysis in the tens of thousands of instructions per second has led to the use of re...

This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP's) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earli...

High performance processor designs use techniques such as pipelining, multiple execution units, register renaming, bypass paths, and branch prediction to meet their goals. These techniques make them susceptible to design errors that are triggered only when executing complex sequences of instructions. We introduce a language called SIGL for specifyi...

Various defects during fabrication have been shown in the literature to introduce delay faults in logic circuits. This paper analyzes the effects of these defects on the normal operation of logic circuits with the goal of developing an appropriate model for these faults. Single and multiple delay faults in this model are analyzed to determine if th...

AC testing of integrated circuits and assemblies is gaining importance as the trend continues in favor of fewer defects shipped and use of higher performance technologies. While there is a large body of literature on test generation and fault simulation related to ac test, the optimization of timing on the tester has been unexplored. This paper def...

The use of constraint solving and symbolic execution to generate highly probing test cases is discussed. A system called AVPGEN, which uses such techniques for debugging high-level machine designs and has already proved useful in finding errors, is described. AVPGEN generates large numbers of architecture verification programs. It consists of a gen...

Gate delay faults can represent the effects of common point faults in logic circuits. A gate delay fault model based on the analysis of these effects in the normal operation of logic circuits is developed. The fault model allows for delay faults of both bounded and unbounded size. Techniques have been developed to identify single gate delay faults...

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First Page of the Article

All test generation algorithms make use of symbolic algebra. The symbolic value that most test generators use is `X', to denote the unknown/do not care logic value. The other end of the spectrum is to shade each X differently to fully exploit the information contained in them. This is impractical due to combinatorial explosion that results from suc...

Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected dela...

A method of synthesizing scan designs that are testable with pseudorandom patterns is presented. The logic is first simplified by various transformations in a logic synthesis system. A fault simulator is then used to guide the placement of control points and observation points. In order to reduce the overhead, control points are shared when possibl...

The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A , B , and R . A is the...

An approach to test for delay faults is presented. A variable size delay fault model is used to represent these failures. The nominal gate delays with the manufacturing tolerances are an integral part of the model and are used in the propagation of simplified waveforms through the logic network. The faulty waveforms are functions of the variable-si...

For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using a...

SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very...

Hardware engines (e.g. YSE and EVE) have been built to perform functional simulation of large designs over many patterns. The authors present a method of simulating faults in parallel that is applicable to these hardware simulation engines (and to software simulators with similar characteristics). A notion of independence between faults is used to...

Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when u...

We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very eff...

This paper specifies procedures for defining a monitor circuit that can detect faults in microprogram sequencers. The monitor and the sequencer operate in parallel and errors are detected by comparing outputs from the monitor circuit with outputs from the sequencer. Faults that cause errors in the flow of control are detectable, as well as some fau...

A design-oriented microprocessor laboratory has been developed for two senior-level courses. The laboratory centers around a Motorola 6800-based microcomputer built within the Electrical Engineering Department. It was designed to provide "hands-on" programming experience but, most importantly, to allow a variety of interfacing experiments to be per...

Thesis (Ph. D.)--University of Minnesota, 1983. Includes bibliographical references (leaves 130-134).