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Vasudevareddy Tatiparthi

Vasudevareddy Tatiparthi
BVRIT | BVRIT · Department of Electronics and Communication Engineering

M.Tech Ph.D

About

11
Publications
6,172
Reads
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7
Citations
Citations since 2017
3 Research Items
4 Citations
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Introduction
Dr Tatiparthi Vasudevareddy currently works at the Department of Electronics and Communication Engineering, BVRIT. Vasudevareddy does research in Engineering Education and Electronic Engineering. Their current project is 'MEMS device level modelling.
Additional affiliations
June 2008 - present
BVRIT
Position
  • Professor (Associate)
Description
  • GREAT RESEARCH FACILITIES AVAILABLE FOR DEDICATED RESEARCHES
June 2008 - present
BVRIT
Position
  • Professor (Associate)

Publications

Publications (11)
Conference Paper
Kids may not show interest in the present conventional system of learning and teaching methods and may not focus. To enhance the existing methods we propose an approach “DIGI SLATE” which teaches them in a passionate way. where they can trace alpha numeric’s on a touch panel under which the led board is placed, where the alpha numeric’s are display...
Research Proposal
Full-text available
The wide utilization & acceptance of low power devices leads to drastic growth in the miniaturization of electronic.The performance of these low power devices on par with the efficiency, But the limitations of the devices are only power and delay, as the devices are operating under the sub threshold operations. SRAM is one of the major component in...
Research
Full-text available
As technology is increasing rapidly, the usage of low power devices has become more usable. One among such is transmission gate 8T SRAM. Static random access memory has now a day's become an important feature in the VLSI chip design. SRAM has become a sustainable research due to its fast development for low power. Static random access memory plays...
Conference Paper
Full-text available
Abstract: Built-In Self-Repair (BISR) with Redundancy is an effective yield enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address -Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four...
Research
Full-text available
This paper provides an overview of the security in the System Architecture Evolution (SAE) / Long-Term Evolution (LTE) system. Security is an integral part of SAE/LTE with improvements over the Third Generation (3G) system. This paper reviews the SAE/LTE system architecture, and discusses the security requirements, algorithms, Authentication and Ke...
Article
Full-text available
This paper demonstrates the design of low voltage, low power CMOS op-amp using DTMOS technique for low-power applications. The design goal is to achieve high gain, phase margin and minimum power dissipation at lower supply voltage. DTMOS transistor is proposed in this paper for the design of op-amp which replaces the normal CMOS transistors for des...
Article
Full-text available
Ultra Low Power is one of the major concern in VLSI Industry recent years. One of the technique which used to improve the concept is Sub-threshold Logic Design. A Number of researchers considering this technique for developing ultra low power applications. The proposed paper is using Sub-threshold logic design for memory devices such as SRAM and ob...
Conference Paper
Full-text available
FPGA based solutions become more common in embedded systems these days. These systems need to communicate with external world. Considering high-speed and popularity of Ethernet communication, developing a reliable real-time Ethernet component inside FPGA is of special value. To that end, we present a new solution for FPGA Gigabit Ethernet communica...

Questions

Questions (2)
Question
I am a bit confused at what are the parameters that can vary by changing the technology from 45 to 32nm of 6T  SRAM design technology??
and also what are the parameters that can vary by changing the technology from 45 to 32nm of  8T SRAM design technology??

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