Valery Salauyou

• Bialystok University of Technology

W książce omówiono zastosowanie popularnego języka projektowego SystemVerilog w syntezie systemów cyfrowych. Główne elementy syntaktyczne i konstrukcje języka są opisane w sposób wystarczający do ich praktycznego zastosowania. Każda konstrukcja językowa jest opatrzona przykładem. Prezentacja materiału nie jest związana z konkretną bazą sprzętową an...

The paper presents an application of the ASMD-FSMD technique for designing high-performance digital circuits on the example of an implementation of sequential multipliers in reconfigurable FPGA devices. The method primarily enables multiple operations on the same variable within a single clock cycle. The experiments were conducted using the Quartus...

Modern reconfigurable systems are typically implemented in field-programmable gate arrays (FPGAs) based on look-up tables (LUTs). Finite state machines (FSMs) perform the functions of control devices and are integral to reconfigurable systems. When designing reconfigurable systems, the problem of optimizing the area and performance of FSMs often ar...

The subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages (HDLs) that prevent failures in the state register and in the input vector of the FSM. The tasks t...

The subject matter of this article is a control system for unmanned aerial vehicles (UAVs) whose mathematical model is a finite state machine (FSM). The goal is to develop FSM structural models that enable (1) detection of multiple faults of FSM elements caused by an electromagnetic pulse or laser beam, and (2) prevent negative impacts on the contr...

The fault detection is an important task in the design of fault-tolerant finite state machines (FSMs). The paper describes structural models of Moore FSM for detecting multiple faults in various elements of the FSM and preventing their negative impact on the controlled object. The considered structural models allow detecting invalid transitions bet...

The fault detection is an important task when designing fault-tolerant finite state machines (FSMs). This paper presents structural models of the Moore FSM for detecting faults and preventing their negative impact on the controlled object. The considered structural models allow detecting invalid transitions between FSM states, invalid input and out...

T he book presents issues of designing embedded systems in FPGAs using their description in Verilog and IP memory blocks of various types: single-port and two-port RAM, ROM, FIFO, LIFO, and shift registers in embedded memory blocks. Several methods of designing control systems are discussed: in the form of a microprogrammed automaton with a graph s...

The ASMD-FSMD technique for designing digital devices consists in building an algorithmic state machine with data-path (ASMD) describing the behavior of the device, and creating a project code in Verilog language in the form of a finite state machine with data-path (FSMD). The ASMD-FSMD technique significantly reduces the design time and increases...

Different strategies for the combination of merging and splitting transformation procedures for incompletely specified finite state machines implemented on field-programmable logic devices are offered. In these methods, such optimization criteria as the speed of operation, power consumption and implementation cost are considered already in the earl...

T his book presents one of the most widely used hardware description languages, Verilog. It describes in detail the syntax and constructs of Verilog, from the point of view of their practical application. Each of the presented constructs is illustrated by a code example and its register-transfer level implementation. The presented material is not l...

Currently, there is a reduction in the lifetime of embedded systems. This requires a shorter time to market, that is, a shorter time to design system-on-chip (SoC) whose core component is the embedded processor. This paper discusses three techniques for designing embedded processors on the field programmable gate array (FPGA): the traditional appro...

Recently, there has been an increase in the complexity of digital device designs and an increase in the requirements for the development time and the reliability of the products. The developing new techniques for designing digital devices is one of the directions to solve this problem. This paper proposes the technique for designing digital devices...

The paper proposes a new technique designing digital devices based on finite state machines with datapath (FSMD), when the functioning of the device is described in the form a chart of an algorithm state machine with datapath (ASMD). The ASMD-FSMD technique is compared to the traditional approach when synchronous multipliers are implemented on a fi...

Recently, there has been, on the one hand, an increase in the complexity of digital device designs and, on the other hand, an increase in the requirements for the development time and the reliability of the designs. One of the directions of solving this problem is developing new techniques for designing digital devices.This paper proposes a new tec...

The synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms...

Structural models of finite-state machines (FSMs) that make it possible to use the values of the output variables for encoding the internal states are studied. To minimize the area (the parameter area is used to denote cost in the context of this paper) of FSM implementation, it is proposed to use the structural model of the class D FSM. A method f...

Coding techniques in Verilog HDL of finite state machines (FSMs) for synthesis in field programmable gate arrays (FPGAs) are researched, and the choice problem the best FSM coding styles in terms of an implementation cost (area) and a performance (speed) are considered. The problem is solved empirically by executing of experimental researches on th...

A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of...

In this paper, we propose the method of FSM synthesis on field programmable gate arrays (FPGAs) when input variables are used for state assignment. For this purpose we offer a combined structural model of class A and class E FSMs. This paper also describes in detail the algorithms for synthesis a class AE FSM which consists of splitting of internal...

A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. The method can be easily included in designing the flow of digital systems in FPGA. Estimations of the number of LUT levels are presented for an implementation of FSM transition...

The article considers the general synthesis technique of hierarchical tree structures on FPGA/SoC for binary comparators. Designing of first level comparators is given. The best hierarchical comparator structure for the specific FPGA/SoC family is found empirically by experimental researches. The offered method allows reducing an area from 5.3% to...

This paper presents two heuristic methods of encoding the internal states of finite state machine to minimize the power consumption: a fixed and a variable code length. The second approach has low computational cost. Experimental researches show a significant reduction in energy consumption in the first method, compared to the algorithm NOVA averag...

The paper describes the problem of synthesis of finite state machines for programmable logic. A specific feature of the described problem is using of the values of output variables as a code of internal states. To solve this problem a combined model of Mealy and Moore machines is used. The main difference between the proposed approach and the well-...

This paper describes the problem of synthesis of finite automata on programmable logic. A special feature of the method is application of values of output variables as a code or as a part of code of internal states of a finite automata. In order to solve the problem a common model of Mealy and Moore machines was used. The main difference of this ap...

The present state of research in the area of low-power design methodologies and mechanisms of power dissipation in digital circuits are considered. The choice of the corresponding model of power estimation is demonstrated to exert a significant effect on quality, cost, and performance of designed digital circuits. An analysis of various power estim...

New algorithms of coding the internal states of finite-state machine (FSM) have been (were) proposed. These algorithms make it possible to reduce the power consumption of sequential devices at the stage of their designing. The algorithms presented are based on solving the minimization problem of the switching activity of FSM memory elements that di...

In this paper we deal with the problem of the finite states machine's (FSM) state assignment. CMOS- based digital circuits dissipate a power only during a transition at the output. Therefore one of the methods of the power minimization is to reassign the FSM states. We discuss the methods such as column-based and annealing-based as well as propose...

W artykule przedstawiono pakiet programów ZUBR automatyzacji projektowania logicznego systemów cyfrowych na programowalnych układach logicznych. Opisano metody syntezy automatów skończonych zaimplementowane w pakiecie ZUBR. Wyniki badań eksperymentalnych potwierdzają efektywność opracowanych metod w porównaniu do metod stosowanych w pakietach przem...

W pracy przedstawiono pakiet programów ZUBR służący do optymalizacji procesu projektowania systemów cyfrowych na bazie logiki programowalnej. Opisano nowe metody syntezy układów kombinacyjnych i automatów skończonych zaimplementowane w pakiecie ZUBR. Przedstawiono niektóre rezultaty badań eksperymentalnych pakietu i porównano je z wynikami otrzyman...