Vacius Jusas

Vacius Jusas
Kaunas University of Technology · Department of Software Engineering

PhD

About

89
Publications
28,465
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
621
Citations
Introduction
Additional affiliations
June 2006 - present
Kaunas University of Technology
Position
  • Professor (Full)

Publications

Publications (89)
Article
Full-text available
Privacy and data security have become the new hot topic for regulators in recent years. As a result, Federated Learning (FL) (also called collaborative learning) has emerged as a new training paradigm that allows multiple, geographically distributed nodes to learn a Deep Learning (DL) model together without sharing their data. Blockchain is becomin...
Article
Full-text available
The COVID-19 pandemic has forced much education to move into a distance learning (DL) model. The problem addressed in the paper is related to the increased necessity for the capacity of data, secure infrastructure, Wi-Fi possibilities, and equipment, learning resources which are needed when students connect to systems managed by institutional, nati...
Article
Full-text available
Gamification of education is considered to have the capacity to increase students’ engagement in a learning process; to drive learning and skills acquisition; and creates changes for more sustainable behavior. Sustainable behavior is especially important in studying the initial courses at a university. Object-oriented programming (OOP) is such a co...
Article
Full-text available
Distance learning plays a significant role in solving the problem of the sustainable development of society. Unfortunately, the development and implementation of distance courses are still carried out intuitively, which does not allow practical implementation of effective mathematics methods and slows down the introduction of breakthrough technolog...
Article
Full-text available
This paper introduces a blockchain-based federated learning (FL) framework with incentives for participating nodes to enhance the accuracy of classification problems. Machine learning technology has been rapidly developed and changed from a global perspective for the past few years. The FL framework is based on the Ethereum blockchain and creates a...
Article
Lack of guidelines for implementing distance learning, lack of infrastructure, lack of competencies, and security‐related problems were the challenges met during the pandemic. These challenges firstly fall on the administration of a higher education institution. To assist in solving the challenges of the pandemic for the administration of a higher...
Article
Full-text available
Digital forensics practitioners encounter numerous new terminologies during time-intensive digital investigation processes because of the explosive growth of the web, an immense amount of data, and rapid changes in technology. In such a scenario, the time needed to find and interpret the cause of the potential digital incident can be affected by th...
Article
Full-text available
Acquiring a clear perspective of events and artefacts that occur over time is a challenging objective to accomplish in digital forensics. Reconstruction of the timeline of events and artefacts, which enables digital investigators to understand the timeline of digital crime and interpret the conclusion in the form of digital evidence, is one of the...
Article
Full-text available
The essential task of a Brain-Computer Interface (BCI) is to extract the motor imagery features from Electro-Encephalogram (EEG) signals for classifying the thought process. It is necessary to analyse these obtained signals in both the time domain and frequency domains. It is observed that the combination of multiple algorithms increases the perfor...
Article
The motor imagery (MI) based brain-computer interface systems (BCIs) can help with new communication ways. A typical electroencephalography (EEG)-based BCI system consists of several components including signal acquisition, signal pre-processing, feature extraction and feature classification. This paper focuses on the feature extraction step and pr...
Article
Full-text available
The planned in advance cyber-attacks cause the most damage for the users of the information systems. Such attacks can take a very long time, require considerable financial and human resources, and therefore, they can only be organized by large interest groups. Furthermore, current intrusion detection systems, intrusion prevention systems and intrus...
Article
In Lithuania, there are accumulated large amounts of fertilizer by-product – phosphogypsum and there is a lack of sources of natural gypsum. Recycling of by-product is one of the effective solutions of its disposal problem. The paper describes an investigation of the hydration behavior of a phosphogypsum with zeolite (hydrosodalite) addition using...
Article
Full-text available
The increased popularity of brain-computer interfaces (BCIs) has created a new demand for miniaturized and low-cost electroencephalogram (EEG) acquisition devices for entertainment, rehabilitation, and scientific needs. The lack of scientific analysis for such system design, modularity, and unified validation tends to suppress progress in this fiel...
Chapter
In this paper the use of convolutional neural networks (CNN) is discussed in order to solve four class motor imagery classification problem. Analysis of viable CNN architectures and their influence on the obtained accuracy for the given task is argued. Furthermore, selection of optimal feature map image dimension, filter sizes and other CNN paramet...
Article
Full-text available
The paper focuses on and examines the issues and problems related to remote evaluation of software engineering competences using progressive competence representation model. Authors suggested original approach for Master Program in Software Engineering competence evaluation as a combination academic competences and professional competences from Eur...
Article
Full-text available
In this paper the use of a novel feature extraction method oriented to convolutional neural networks (CNN) is discussed in order to solve four-class motor imagery classification problem. Analysis of viable CNN architectures and their influence on the obtained accuracy for the given task is argued. Furthermore, selection of optimal feature map image...
Article
Full-text available
Digital triage is the first investigative step of the forensic examination. The digital triage comes in two forms, live triage and post-mortem triage. The primary goal of the live triage is a rapid extraction of an intelligence from the potential sources. The live triage raises legitimate concerns. The post-mortem triage is conducted in the laborat...
Article
Full-text available
Abstract.- This research provides analysis of existing models for competence evaluation and proposes a software engineering competence remote evaluation process model. We separate competences into two domains: professional and academic. The model is developed and implemented for e-CF professional competences and academic competences evaluation for...
Article
We presented nine new black box delay fault models for non-scan sequential circuits at the functional level, when the primary inputs and primary outputs are available only. We examined the suggested fault models in two stages. During the first stage of the experiment, we selected the best two fault models for further examination on the base of crit...
Article
Full-text available
The BitTorrent client application is a popular utility for sharing large files over the Internet. Sometimes, this powerful utility is used to commit cybercrimes, like sharing of illegal material or illegal sharing of legal material. In order to help forensics investigators to fight against these cybercrimes, we carried out an investigation of the a...
Article
Full-text available
The BitTorrent Sync client application is the most progressive development in the BitTorrent family. Nevertheless, it can be used for the activities that draw the attention of the forensics invetigators. The BitTorrent Sync client application employs quite largely the encryption for sending data packages. The initiation of the activity is carried o...
Article
Full-text available
The BitTorrent client application is a popular tool to distribute the large files over the Internet. However, the utility can be used for the illegal distribution of some files. Such an activity is considered as a cybercrime. In order to aid the forensics investigator to fight against the cybercrimes we carried out the research, during which we inv...
Article
Full-text available
The paper presents a novel extension of the Huang's Empirical Mode Decomposition (EMD) method, called BoostEMD, that allows calculating higher order Intrinsic Mode Functions (IMFs) that capture higher frequency empirical mode oscillations (empiquencies) in the EMG (electromyography) data. We describe the use of the second order IMFs for denoising p...
Article
Full-text available
The Internet of Things (IoT) is a novel design paradigm, which allows communication among different kinds of physical objects over the common Internet infrastructure. Operations and application models of the IoT, which differ from the traditional networks, have brought great challenges and opportunities to digital forensic technology. In this paper...
Conference Paper
Full-text available
The Internet of Things and Services (IoT&S) is a novel-networking paradigm, which allows the communication among various types of physical objects and people over the Internet. Operations and application models of IoT&S are different from the traditional networks have brought great challenges and opportunities to digital forensic technology. In thi...
Article
The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and stat...
Article
Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. Each process in VHDL is executed in parallel. This concept introduces problems of how to test and verify complex systems. We present the new framework TestBenchMulti that is able to generate tes...
Article
Full-text available
Electroencephalography (EEG) is widely used in clinical diagnosis, monitoring and Brain - Computer Interface systems. Usually EEG signals are recorded with several electrodes and transmitted through a communication channel for further processing. In order to decrease communication bandwidth and transmission time in portable or low cost devices, dat...
Article
Full-text available
BitTorrent client application is a popular tool to download large files from Internet, but this application is quite frequently used for illegal purposes that are one of the types of cybercrimes. If order to fight against this type of cybercrime we carried out the research, during which we investigated the evidences left by BitTorrent client applic...
Conference Paper
This work analyzes several feature extraction methods used in today’s EEG BCI (electro-encephalogram brain computer interface) classification systems. Comparison of multiple EEG energy algorithms is presented for solving a 4-class motor imagery BCI classification problem. Furthermore, multiple feature vector generation techniques are employed into...
Conference Paper
Electroencephalogram (EEG) is a popular method for measuring the electrical activity of the brain, and diagnose a variety of neurological conditions such as epileptic seizure. Furthermore, most Brain - Computer Interface systems provide modes of communication based on EEG, usually signals are recorded with several electrodes and transmitted through...
Article
Hardware Description Languages (HDL) like VHDL are used to design and simulate programmable logic devices. Usually the description of the device under test consists of several processes. This concept introduces problems of how to test and verify complex systems. In this paper, we present a new framework called TestBenchMulti that is able to generat...
Article
Full-text available
We propose a method for reconstruction of the high-dimensional phase space of the electroencephalography (EEG) signal. The method is based on the selection of positive trajectories from the phase space, distance-adaptive sampling of the negative trajectories from the phase space, classification of trajectories in the phase space, and reconstruction...
Article
Verification is an important part of the chip design process. Design is usually represented in hardware description language (HDL). Contemporary HDLs have constructs that are characteristic to software programs. Therefore, the methods to automatically generate test for software programs can be applied to generate test for HDL models. One of such me...
Article
Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model ca...
Conference Paper
Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. We present an algorithm that achieves high code coverage by analyzing the finite state machine (FSM), and control flow graph (CFG) that are constructed from the source code. The symbolic executi...
Article
Full-text available
Brain - Computer Interface (BCI) systems require intensive signal processing in order to form control signals for electronic devices. The majority of BCI systems work by reading and interpreting cortically evoked electropotentials across the scalp via an electro encephalogram (EEG). Feature extraction and classification are the main tasks in EEG si...
Conference Paper
Full-text available
Brain Computer Interface (BCI) systems perform intensive processing of the electroencephalogram (EEG) data in order to form control signals for external electronic devices or virtual objects. The main task of a BCI system is to correctly detect and classify mental states in the EEG data. The efficiency (accuracy and speed) of a BCI system depends u...
Article
The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the re...
Conference Paper
Full-text available
Brain-Computer interface (BCI) systems require intensive signal processing in order to form control signals for electronic devices. The majority of BCI systems work by reading and interpreting cortically evoked electro-potentials across the scalp via an electro-encephalogram (EEG). An important factor affecting the efficiency of BCI is the number o...
Conference Paper
The major challenge for the semiconductor industry is to design devices in short time with complex logical functionality. At the very top of the list of challenges to be solved is verification. The goal of the verification is to ensure that the design meets the logical functional requirements as defined in the logical functional specification. Veri...
Article
The functional delay-fault models, which are based on the input stimuli and correspondent responses at the outputs, cover transition faults at the gate level quite well. This statement forms the basis for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to select the...
Article
Full-text available
Brain-Computer Interface (BCI) systems require application of complex analysis, signal processing, denoising, feature extraction, dimensionality reduction and classification methods on acquired raw electroencephalogram (EEG) data to allow for useful operation. In this paper, we consider application of nonlinear operators such as Taeger-Kaiser Energ...
Article
Full-text available
E. Bareisa, V. Jusas, K. Motiejunas, R. Seinauskas, L. Motiejunas. Application of Preselection of Test Subsequences in Sequential Test Generation for Functional Delay Faults // Electronics and Electrical Engineering. - Kaunas: Technologija, 2012. - No. 2(118). - P 33-37. Testing of high-performance circuits for timing failures is becoming very impr...
Article
The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as,...
Article
High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. The latest research shows that functional tests designed using random test generation exhibit good transition fault coverages. In the paper, we investigated the possibilities of improving random test generation for at-speed testing of non-scan...
Article
Full-text available
In this paper, we report a hardware implementation scheme and results of a Loeffler algorithm based 2-D discrete cosine transform codec. This codec performs a full 2-D DCT encoding and 2-D IDCT decoding. It is fully functional, capable of being used in any hardware coding algorithm. The Loeffler algorithm is one of the newest and most effective fas...
Article
Full-text available
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based o...
Article
We investigated the influence of the random generation methods to the results of the functional delay test generation. There are the three possibilities: random generation of values 0 and 1 when the probability for the appearance of each value is 50% in every bit of test pattern; random generation of large integer values, which then are split into...
Article
Full-text available
The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. These fault models form one joint functional fault model. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circui...
Article
Full-text available
The paper investigates the possibilities of application of random generated test sequences for at-speed testing of non-scan synchronous sequential circuits. Our research shows that relatively long random test sequences exhibit better transition fault coverages than tests produced by deterministic ATPG tools. We proposed an approach for dividing of...
Article
The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. Th...
Article
Full-text available
The testing problem is becoming the most crucial part of overall design process that delays the time-to-market of the digital devices. In order to alleviate the test generation complexity and to reduce the time-to-market, one needs to begin the test design at higher levels of abstraction. In this paper a new approach for static functional test enri...
Article
Full-text available
The quality of delay testing focused on small delay defects is not known when transition fault model is used. The paper presents a method that evaluates the quality of the delay test according to the covered paths of the circuit and constructs the paths, which could be used as the input to the path delay test generator. All the constructed paths ar...
Article
Full-text available
The testing phase is becoming the most crucial part of the overall design process, which delays the time-to-market of the digital devices. In order to reduce the complexity of test generation and to decrease the time-to-market, one needs to begin the test design at higher levels of abstraction. In this paper a new approach for functional delay test...
Article
We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input–output pin pair and an input–input–output pin triplet fault models. The basic properties of these models are analyzed. Random test gene...
Conference Paper
With ever shrinking geometries, growing density and increasing clock rate of chips, delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The aim of this paper is to explore how functional delay tests constructed at algorithmic level detect transition faults at gate-level. Main attention was...
Article
Full-text available
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. The purpose of this paper is to assist to designer in the decision making how to te...
Article
Full-text available
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. In this paper we consider the impact of circuit realization on the fault coverage o...
Article
Full-text available
Compact test sets are very important for reducing the cost of testing the very large scale integrated circuits by reducing the test application time. In this work we presented a new procedure of functional static-based test transformation into functional delay test that allows improving test compaction. Experimental results for ISCAS'85 and ITC'99...
Article
Full-text available
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault...
Article
Full-text available
The analysis how the functional fault tests detect structural faults at gate-level shows that the stuck-at fault coverage is much higher than transition fault coverage. The aim of the paper is to discover the reasons of this phenomenon and to propose the techniques of functional delay test quality improvement. We suggest, by transformation of pin p...
Article
Full-text available
The software prototype model can be used for the generation of the verification test. The input stimuli, which form essential activity vectors, are selected from randomly generated ones oil the base of software prototype. The essential activity vectors correspond to the terms of logical functions of output the existence of which is tested during th...
Conference Paper
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The main problem is the quality assessment of the functional test because the implementation of the circuit is not available yet. The paper present...
Conference Paper
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are c...
Article
Full-text available
The aim of this paper is to explore some features of the functional test generation prob- lem, and on the basis of the gained experience, to propose a practical method for functional test generation. In the paper presented analysis of random,search methods and adjacent stimuli gener- ation allowed formulating a practical method,for generating funct...