Usha Mehta

• Ph.D. in VLSI Design
• Professor (Full) at Nirma University

Finite State Machines (FSMs) are considered the “brain”, which drives and controls the integrated circuit or system functionalities. Therefore, radiation or glitch-induced failures in FSMs can have severe consequences on the circuit or system functionalities, where these FSMs are performing control operations. Generally, every FSM has some illegal...

One of the alternatives to the current silicon technology, Complementary Metal Oxide Semiconductor (CMOS) is Quantum-dot Cellular Automata (QCA). Test generation is an unavoidable process in the CMOS design flow. This possibility of test generation must be explored and applied to the QCA as the QCA is a novel and nanoscale technology. Therefore, in...

Contemporary system-on-chip (SoC) architecture integrates various extremely sensitive hardware components that are required to be secured from unwanted intrusion. Therefore, modern SoC design has to be included with countermeasures against attacks to sensitive hardware components. The attacks can be implemented through noninvasive side channels suc...

Process variation has been aroused as a prospective design concern in current nano-scale integrated circuits (ICs). With the shrink in technology size, graphene nano-ribbon has proven to be a potential futuristic material for on-chip interconnect system. This research paper addresses the stochastic parameter variability on novel on-chip interconnec...

Hardware security is becoming a major concern and threat due to the emerging hardware Trojan attacks. The threat poses due to malicious hardware Trojans during SoC life cycles are major causes of a security breach, financial theft and malfunctioning of SoCs. An attacker may mount such an attack by keeping the goal of operation failure or informatio...

Advanced encryption standard (AES) crypto‐algorithm design can be implemented in software and hardware. No known attacks are available that can break the AES with brute force or cryptanalysis in finite time. However, when the AES is implemented in hardware, test infrastructure such as scan chain, stimuli decompressor, response compactor and built‐i...

Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit Technology considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology. Being at molecular scale, defects are more likely to occur in QCA devices. Therefore, the substantial development of QCA-oriented defec...

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test...

The Design for Testability (specifically scan designs) is standard testing techniques for Digital cores for achieving high fault coverage and to provide better controllability and observability. However, such test architectures in the chip containing secret data mostly becomes the instrumental for secret information leakage. The attacker may use di...

Considering the limitations of CMOS technology, the Quantum-dot Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit (IC) Technology. A lot of work is being carried out for design, fabrication and testing of QCA circuits. In this paper, we have worked on defect analysis, fault models development and deriving various...

For a stated core, the test time changes in a staircase pattern with the width of Test Access Mechanism (TAM). The core test time cannot decrease all time with increase in TAM width. However, the test time can always be diminished with increasing the test clock speed but clock speed cannot be increased beyond power limits. Here, a new method is pro...

In the near future the era of Beyond CMOS will start as the scaling of the current CMOS technology will reach the fundamental limit. QCA (Quantum-dot Cellular Automata) is the transistor less computation paradigm and viable candidate for Beyond CMOS device technology. The complete state of art survey on QCA is presented in this paper. This paper ad...

Traditionally, Hardware is considered as root of trust. Software generally builds on top of the hardware. By emerging Hardware Trojan attacks, this trust seems to be violated. Hardware Trojan is any addition or modification to a circuit or a system with malicious intention. Trojan can cause change or control over functionality in circuit or it may...

Defects and hence faults are present in the QCA (Quantum-dot Cellular Automata) nanotechnology devices and circuits. Hence it is important to test these nanotechnology devices and circuits. This paper investigates the new properties for the test generation for the QCA device majority voter. A method of test generation is developed to find the singl...

QCA (Quantum-dot Cellular Automata) is the most capable future nanotechnology for computing. Defects are most likely to occur in QCA devices due to the nanoscale Faults caused by these defects must be analyzed. This paper implement the QCA combinational circuit, half adder for which fault analysis is carried out. This paper presents the fault analy...

System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today's integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That's why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge abou...

Digital to analog converter is widely used mixed-signal circuit. Testing of analog and mixed signals faces lots of challenges due to the wide range of circuits and unavailability of one appropriate fault model. SAF (stuck_at_Fault), Stuck_open and stuck_short fault model at transistor level is used in this paper. Further these fault models are used...

Radiation Hardened By Design (RHBD) combinational circuits/primitive gates using 0.18um CMOS Technology is developed for Space application with help of Cogenda TCAD software suite. The proposed combinational cells are investigated for radiation simulation using three dimensional (3D) device structure. Single Event Transient (SET) caused by proton,...

In the current scenario of IP core based SoC, to reduce the test time and test cost, the test data is preprocessed and compressed heavily. This compressed test data are transferred from Automatic Test Equipment (ATE) to chip under test through a serial communication link and will be decompressed on-chip before applying to actual DUT. If there is a...

To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The pr...

The reduction in hardware requirement for any application does not only guarantee the reduction of chip area but also significantly reduces the corresponding power consumption and delays. Hence, any heuristic used to reduce the hardware requirement for given logic is always well justified. In this paper, the number of pass gates required to impleme...

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault mode...

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault mode...

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Test Power is the major issues for the external testing of IP core based SoC. From a large pool of diverse available techniques for switching activity reduction during the external testing, only those schemes like ‘don't care bit filling’ and ‘reordering’ which do not require any modification in internal structure and do not demand use of any test...

Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the flip-flops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the g...

Test power and test time have been the major issues for current scenario of VLSI testing. The test data compression is the well known method used to reduce the test time. The don't care bit filling method can be used for effective test data compression as well as reduction in scan power. In this paper we describe the algorithm for don't care assign...

Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reorderin...

In this paper it is observed that the test data compression environment (TDCE) parameters: compression ratio and area overhead of code based data compression techniques in statistical method like Huffman coding, selective Huffman coding, optimal Huffman coding, variable length input Huffman coding(VIHC) and split-VIHC and conclude that split VIHC m...

Test Power is the major issues for the external testing of IP core based SoC. From a large pool of diverse available techniques for switching activity reduction during the external testing, only those schemes like 'don't care bit filling' and 'reordering' which do not require any modification in internal structure and do not demand use of any test...

Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of...

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the pr...

For SoCs (Sea of Cores!) which contains a large amount of IP cores with pre computed test data, the code based test data compression scheme is more suitable as it does not require any knowledge of internal nodes of IP. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this...

Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for cu...

This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method “Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don't Care Bit Filling” is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power o...

The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don't care bit filling based on nature of runs are proposed. These methods are used here to predict the maximum compression based on entropy relevant to different run length base...

Test data compression is a basic necessity for today's test methodology with reference to test cost and test time. This paper presents a compression/decompression scheme based on frequency dependant bit appending of test vector used with statistical codes. In the proposed scheme, the emphasis is not only on data compression but it aims the data com...

The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and...

Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in past. Run length coding is one of t...

With the increase improvement in VLSI design and progressive complication of circuits, an efficient technique for test pattern generation is necessary with the intension of reducing number of faults and with use of testability measures. Using the fault equivalence method, the number of faults are reduced. The line justification and error propagatio...

Scan chain design is a popular design-for-test technique for testing of sequential circuits. Significant amount of power is consumed during loading and unloading of scan chains due to weighted transitions. As the power consumption in the test mode is quite high compared to normal circuit operation, the test power has become the prime concern for cu...

As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests and corresponding data volume increase with each new fabrication process technology. The demand goes to well beyond 100X tester cycle reduction considering new fault models. The test data c...

Increase in transistor density has a great impact on testing as well as design. In worst case, test complexity increases exponentially with number of transistors and number of flipflops. The amount of data and complexity of data generation required to test ICs is growing rapidly in each new generation of technology. The testing of any circuit is ba...

It is well known that verification today constitutes about 70% to 80% of the total design efforts, thereby making it the most expensive component in terms of cost and time, in the entire design flow of any ASIC. A number of academic and industrial research laboratories have been carrying out research on verification reuse and static and dynamic met...