Tony Do

• Agency for Science, Technology and Research (A*STAR)

Neuromorphic computing is promising to achieve unprecedented energy efficiency by emulating the human brain’s mechanism. Conventional neuromorphic accelerators employ split-and-merge method to map spiking neural networks’ inputs to surpass the fan-in capabilities of a single neuron core. However, this approach gives rise to the risk of accuracy com...

Binary Neural Network (BNN) accelerators are attractive solutions for Artificial Internet-of-Things (AIoT) applications thanks to the compact models and low computational cost while maintaining satisfactory classification performance. Various analog/mix-signal compute-in-memory macros have been proposed to boost the energy efficiency of binary conv...

Convolutional Neural Network (CNN) is widely acknowledged as an effective machine learning model for various detection and recognition tasks. However, CNN often requires a significant amount of hardware resources and is high in its power consumption. This hinders the widespread deployment of CNN model in embedded systems and wearable devices. There...

Crossbar-based neuromorphic chips promise improved energy efficiency for spiking neural networks (SNNs), but suffer from the limited fan-in/fan-out constraints and resource mapping inefficiency. In this paper, we propose a new hardware mechanism to enable configurable combination of cores, called coreset. Using this hierarchical method, our end-to-...

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, w...

Always-on keyword spotting (KWS) hardware is gaining popularity in ultra-low power IoT applications where specific words are used to wake up and activate the power hungry downstream system. This work proposes a low power KWS engine with a power-optimized Mel-frequency cepstral coefficients (MFCC) feature extraction module and a memory-optimized lon...

With the ability to generate different spiking patterns, Izhikevich model has well been considered a computationally efficient and biologically plausible neuron model for applications such as brain dynamic behavior study. This paper presents a low-cost, high-throughput digital hardware design for Izhikevich neuron model. The proposed design require...

Neuromorphic (NC) designs have gained significant interest in recent hardware research due to its low-power consumption. Low-power and low-latency router design is one of the most critical component to ensure NC hardware’s scalability and energy efficiency. Various router designs have been proposed to achieve high performance. However, this leads t...

This paper presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a large...

This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are util...

Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boos...

This paper presents a power and area efficient processor for real-time neural spike-sorting. We propose a robust spike detector (SD), a feature extractor (FE), and an improved k-means algorithm for better clustering accuracy. Furthermore, time-multiplexing architecture is used in SD for dynamic power reduction. A customized 39kb 8T SRAM is also imp...

In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by u...

Directing cell behaviour using controllable, on-demand non-biochemical methods, such as electrical stimulation is an attractive area of research. While there exists much potential in exploring different modes of electrical stimulation and investigating a wider range of cellular phenomena that can arise from electrical stimulation, progress in this...

Hemocompatibility, anti-inflammation and anti-thrombogenicity of acellular synthetic vascular grafts remains a challenge in biomaterials design. Using electrospun polycaprolactone (PCL) fibers as a template , a coating of polypyrrole (PPy) was successfully polymerized onto the fiber surface. The fibers coated with heparin-doped PPy (PPy-HEP) demons...

Applications such as Logging-While-Drilling (LWD), automotive, and aerospace systems require electronics whose operating temperature is much higher than that of conventional consumer electronics. One of the most critical functional blocks for high temperature operation is memory due to the significantly increased leakage. This paper explains two di...

8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by '1' or '0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that di...

An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS...