Tomás Bautista

Tomás Bautista
Universidad de Las Palmas de Gran Canaria | ULPGC · Department of Electronic and Automatics Engineering

Doctor of Engineering

About

46
Publications
2,102
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248
Citations
Additional affiliations
October 1992 - present
Universidad de Las Palmas de Gran Canaria
Position
  • Lecturer

Publications

Publications (46)
Article
Full-text available
In this paper, a novel application of the Nondominated Sorting Genetic Algorithm II (NSGA II) is presented for obtaining the charging current–time tradeoff curve in battery based underwater wireless sensor nodes. The selection of the optimal charging current and times is a common optimization problem. A high charging current ensures a fast charging...
Article
Full-text available
In this paper, a new method for gaining the control of standalone underwater sensor nodes based on sensing the power supply evolution is presented. Underwater sensor networks are designed to support multiple extreme scenarios such as network disconnections. In those cases, the sensor nodes involved should go into standalone, and its wired and wirel...
Article
Full-text available
In this paper, we present a novel charging method for underwater batteryless sensor node networks. The target application is a practical underwater sensor network for oceanic fish farms. The underwater sections of the network use a wireless power transfer system based on the ISO 11784/11785 HDX standard for supplying energy to the batteryless senso...
Article
Full-text available
In this paper, we present the design of a practical underwater sensor network for offshore fish farm cages. An overview of the current structure of an offshore fish farm, applied sensor network solutions, and their weaknesses are given. A mixed wireless–wired approach is proposed to mitigate the problem of wire breakage in underwater wired sensor n...
Article
The AEFishBIT tri-axial accelerometer was externally attached to the operculum to assess the divergent activity and respiratory patterns of two marine farmed fish, the gilthead sea bream (Sparus aurata) and European sea bass (Dicentrarchus labrax). Analysis of raw data from exercised fish highlighted the large amplitude of operculum aperture and bo...
Chapter
In this paper we obtain new detection codes, to determine whether a GPS satellite in particular is visible, using NSGA-II as multi-objective optimization engine. Our approach takes into consideration the length of the code and the sampling frequency in comparison with other approaches found in the literature that fix those design parameters. The ob...
Article
In this paper, the optimization and analysis of threshold configurable regenerative comparators (TC) for use in ultra-low power consumption ADCs is introduced (TC-ADC). Using a 90 nm CMOS technology, the obtained comparator achieves a 77% improvement in terms of power consumption (3μW) when compared with previously published TC comparators, while m...
Article
Full-text available
In this article, we present a flexible and extensible system-level MP-SoC design space exploration (DSE) infrastructure, called NASA. This highly modular framework uses well-defined interfaces to easily integrate different system-level simulation tools as well as different combinations of search strategies in a simple plug-and-play fashion. Moreove...
Article
Purpose – In a global positioning system (GPS) receiver, one of the most time-consuming tasks is to identify and track the visible satellites. The paper aims to propose and examine in detail new and shorter identification patterns or lite pseudo-codes – pseudo-random numbers (PRNs) – that allow GPS receivers to reduce dramatically the computational...
Article
Reducing power consumption leads to improve wireless sensor autonomy, increase battery life, and reduce radiated power. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration uses low ohmic values because high sensitivity and low noise approach. In this work, the piezoresistance values...
Conference Paper
Full-text available
System-level simulation and design space exploration (DSE) are key ingredients for the design of multiprocessor system-on-chip (MP-SoC) based embedded systems. The efforts in this area, however, typically use ad-hoc software infrastructures to facilitate and support the system-level DSE experiments. In this paper, we present a new, generic system-l...
Article
A new static mapping technique is presented that can be integrated in a system-level design tool for modelling and simulating real-time applications onto an embedded multiprocessor system. The results of preliminary experiments indicate that the proposed two-phase mapping approach can achieve a good trade-off between the efficiency in resource usag...
Article
Full-text available
In this paper, we present the modelling of a real-time tracking system on a Multi-Processor System on Chip (MPSoC). Our final goal is to build a more complex computer vision system (CVS) by integrating several applications in a modular way, which performs different kind of data processing issues but sharing a common platform, and this way, a soluti...
Conference Paper
In this paper, we present the strategy for evaluating the performance of a variety of configurations of an architecture template for a computer vision system (CVS). For this study a generic model of an architecture is used to address the modular design of the CVS. This modular nature approach could be used to build a more complex system by integrat...
Article
The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques...
Conference Paper
Full-text available
New generation electronic system-level design tools are the key to overcome the complexity and the increasing design productivity gap in the development of future multiprocessor systems-on-chip. This paper presents a SystemC-based system-level simulation environment, called CASSE, which helps in the modeling and analysis of complex SoCs. CASSE comb...
Conference Paper
Full-text available
Recently, a new programming model and platform interface for MPSoC design and integration called TTL (Task Transaction Level) has been developed and advocated as a standard. In this paper, a specific implementation of the TTL interface named ITCP (Inter-Task Communication Protocol) is presented. ITCP is well suited for both hardware and software im...
Article
Trends in multimedia consumer electronics, digital video and audio, aim to reach users through low-cost mobile devices connected to data broadcasting networks with limited bandwidth. An emergent broadcasting network is the digital audio broadcasting network (DAB) which provides CD quality audio transmission together with robustness and efficiency t...
Conference Paper
Full-text available
As SoC complexity grows new methodologies and tools for system design and time-effective ditsign space exploration are required. In this paper we introduce a tool called CASSE, what stands for Camellia system-on-chip simulation environment. CASSE is a fast, flexible, and modular SystemC-based simulation environment which aims to be useful for desig...
Article
This paper discusses and compares solutions for the issue of signalling and synchronization in the heterogeneous architecture multiprocessor paradigm. The on-chip interconnect infrastructure is split conceptually into a data transport network and a signalling network. This paper presents a SystemC based technique for modelling the communication arc...
Article
In this paper, we present experimental results obtained during the modeling, design, and implementation of a full set of versions of SPARC v.8 Integer Unit cores aimed at embedded applications. VHDL is the description language, Synopsys is the tool used for logical synthesis, and Duet Technologies' Epoch for obtaining the physical layout of the fin...
Conference Paper
A complete quantitative evaluation of the quality of more than one hundred implementations of SPARC processor core and its related circuitry, synthesized from VHDL descriptions, is presented in this paper as a demonstration example for selecting benchmark circuits, synthesis experiments with different tools and technologies, and performance metrics...
Conference Paper
Full-text available
In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies' Epoch has been used f...
Conference Paper
The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final c...
Conference Paper
In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies' Epoch has been used f...
Conference Paper
The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into...
Article
Full-text available
Trends in multimedia consumer electronics, digital video and audio, aim to reach users through low cost mobile devices connected to data broadcasting networks of limited bandwidth. The emergent Digital Audio Broadcasting (DAB) network was developed for the broadcasting of audio and associated data to mobile receivers, offering a maximum data rate o...

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