Tom Schram

imec · Process Technology

Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS 2 field-effect transistors is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individua...

Defective grain boundaries form in semiconductors when deposition approaches do not control crystal grain orientation. This poses existential limitations to fabricating highly performing semiconductor devices with two-dimensional semiconductors for industry’s future Angstrom technology nodes. Today’s monolithic or bottom-up deposition methods do no...

Recent advances in fabricating field-effect transistors with MoS 2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin with the integration of these emerging technologies into FAB-compatible process flows. Just like in the lab research on 2D devices performed in the last decade, focus during development is typi...

Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS2 FETs is presented. In particular, the presence of a limited number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps locate...

Inspired by techniques designed for 3D integration, a die-to-wafer (D2W) transfer method can enable MX 2 -channel devices in a semiconductor fab for either high-performance CFET or hybrid-integrated CMOS. A Collective D2W(CoD2W) technique was successfully developed to transfer epitaxial single-layer MX 2 from sapphire to 300mm device wafers which f...

Direct two-dimensional (2D) material growth is widely considered as the preferred 2D integration approach due to its simplicity and cost-effective fabrication flow. On the other hand, a 2D transfer route enables full wafer-scale integration of epitaxial 2D material and can facilitate new device possibilities. However, the transfer of a wafer size a...

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also cont...

Two dimensional ultrathin layers are considered promising materials to bring new functionalities in nanotechnologies and candidate to replace 3D materials in existing applications. Among this last category, transition metal dichalcogenides (TMDC) like WS 2 , MoS 2 , WSe 2 are viewed as interesting alternative channels for ultra-scaled CMOS technolo...

Large‐area 2D‐material‐based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D‐based circuits for high‐performance logic applications in production is projected to be implemented after the Si‐sheet‐based CFET de...

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected...

the gate stack. Typical cap layers are Al2O3 for pMOSFETs and La-oxide or Mg for nMOSFETs. Besides introducing a dipole layer at the SiO2/high-kappa interface, the in-diffusion of the metal ions may lead to either passivation or generation of traps in the SiO2/high-kappa layer. This paper uses low frequency noise studies to determine the impact of...

To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3 rd dimension at reasonable cost. This pap...

In order to improve the low-frequency noise of input/output (I/O) p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a 5 nm SiO2/2 nm HfO2/5 nm TiN gate stack for DRAM applications, different post-deposition treatments have been investigated. Decoupled Plasma Nitridation with various strengths is compared with an SF6 plasma anneal...

Atomic layer deposited (ALD) tantalum nitride (TaxNy) is evaluated as a barrier against aluminum inside gate metal stacks of metal-oxide-semiconductor field effect transistor (MOSFET) devices. When deposited on hygroscopic oxides, like HfO2, amorphous tantalum nitride (a-TaxNy) is obtained, while deposition on Si or TiN results in polycrystalline T...

When two-dimensional (2D) group–VI transition metal dichalcogenides such as tungsten disulfide (WS2) are grown by atomic layer deposition (ALD) for atomic growth control at low deposition temperatures ( < 450 °C), they often suffer from a nanocrystalline grain structure limiting the carrier mobility. The crystallinity and monolayer thickness contro...

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as...

It is shown that replacing a TiN effective work function metal by TaN results in a pronounced reduction of the low-frequency noise power spectral density (PSD) of thick-SiO <sub xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> input/output (I/O) DRAM peripheral pMOSFETs. The 1/ $f$ noise is originating from carrier number fluctuations, suggestin...

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the character...

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the character...

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning...

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs t...

This paper addresses CMOS integration of thermally stable high-k/metal gate stacks for application to DRAM periphery transistors. We compare four different pattern-ing schemes for the removal of the NFET EWF (Effective Work Function) shifter stack from the PFET area and investigate the effects of plasma exposure during CMOS patterning on the result...

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (N IT ) down to 2 10 ¹¹ cm ⁻² have been demonstrated. [1-3] A clear correlation was established between Ge...

We report on gate-all-around (GAA) N- and P-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24...

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaini...

Mapping and visualization of all degradation modes in both n- and p-channel field effect transistors, specifically devices for dynamic random access memory periphery, is performed in the (VG, VD) bias space applicable for complementary metal-oxide-semiconductor operation. This “all-in-one” approach allows for tracking and studying in parallel all d...

In this work, the negative bias temperature instability (NBTI) performance for HKMG and diffusion and gate replacement (D&GR) input/output (I/O) devices is investigated. Even though NBTI performances of D&GR transistors are aligned with conventional HKMG (high-k/metal gate) integration with thin oxide devices, it is not the case for thick oxide I/O...

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that...

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type...

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (qϕb) MIS contact: Ti/TiO₂/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO₂/n-Si thermal stability study under different electron conduct...

A novel multi work function process is used to demonstrate up to 250 mV effective work function shifts of nMOS devices. The process use SiH4-soak of ALD TiN to change its barrier properties with ALD TiAl. FinFET devices are demonstrated with ~100 mV VT-shift for 24-nm-LG devices resulting in 20× reduction in off-state leakage at unaffected sub thre...

The impact of the implementation of a high-kappa/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack...

The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tunings are needed to keep pace with the request for low leakage and low cost devices combined with the needs of highly per...

Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar and fin based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p...

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high-k, and then by removing the dopant source (dummy doped metal gate) and d...

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm−3) was used as a diffusion source. SiO2 cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO2 exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the hi...

The impact of the implementation of a high-k/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack. Ho...

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si0.55Ge0.45 channel and embedded e:Si0.75Ge0.25 source/drain (S/D), a very significant source current of 625 μA/μm @IOFF=100 pA/μm (at supply voltage VDD=−1 V) is demonstrated. The current improvement...

The oxide trap density profile in DRAM peripheral nMOSFETs with Mg cap and different thermal budgets for in-diffusion of the metal ions has been investigated by low-frequency noise. It is shown that close to the SiO2/HfO2 interface a peak in the trap density is found, which disappears under a high thermal budget. No impact of Mg on the bulk oxide t...

Work function engineering by the introduction of cap layers in a high-k gate stack [1],[2] can be successfully implemented in logic and DRAM peripheral MOSFETs. In the latter case, a so-called Diffusion and Gate Replacement (D&GR) integration scheme has recently been proposed [3], whereby an Al 2 O 3 cap is implemented for tuning the threshold volt...

Accurate determination of contact resistivities ( ) below is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined TLM (RTLM) has a high accuracy at the expense of a more complex fabrication. In this letter, we will present a novel model—multiring CTLM (MR-CTLM) , whi...

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect we...

We have evaluated the impact on the reliability of an innovative process flow, specifically designed for peripheral MOSFETs of DRAM memories. Al and MgO layers are deposited, diffused into the gate stacks of NMOS and PMOS and finally removed. We have demonstrated an anomalous yet predictable PBTI behavior, coupled with a more standard NBTI one. Dec...

We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I ON , +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (L G ) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases acti...

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1 st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (L G ) aro...

This paper reviews the application of low-frequency noise and Random Telegraph Signal (RTS) studies on advanced memory devices, namely, Metal-Insulator-Metal capacitors with SrTiOx as insulator, peripheral transistors for Dynamic Random Access Memories and Resistive Random Access Memory structures. In the first two cases, flicker noise is used to a...

In this work, the potential of the recently demonstrated D&GR (Diffusion & Gate Replacement, [5]) for thick oxide I/O devices integration is investigated. A D&GR integration flow compliant with EOT requirements for I/O devices is demonstrated, with no penalty with regard to HKMG Non D&GR flow in terms of short channel effects and intrinsic transist...

Deep insights into the Off-State Stress (OSS) degradation mechanism on p-MOSFETs with High-K/Metal Gate technology are presented in this paper. Large subthreshold slope degradation, or positive Vth shift is observed in high, or low Vth devices, where both phenomena impact the off current degradation. The OSS degradation mechanism in pMOS is generat...

For the first time, we demonstrate that A-G model extracted from short Vg-accelerated stresses can predict both long term DC and AC NBTI under low and dynamic operation Vg. This is achieved by successfully separating non-saturating defects from the saturating ones, allowing reliable extraction of power exponents needed for long term prediction. Unl...

In this work, the potential of Si 1−x Ge x Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of e...