Taweesak Reungpeerakul

Prince of Songkla University · Department of Computer Engineering

In this study, the high activity Ni–Li–B catalysts were fabricated through wet chemical reduction method. Their morphological structures, crystallinity, surface area and composition were examined by field-emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), Brunauer–Emmett–Teller (BET) method and energy-dispersive X-ray spectros...

The main purpose of this work is to optimize the effects of operating parameters on the yield of products from fast pyrolysis of four palm oil biomasses (empty fruit bunch [EFB], palm shell [PS], palm mesocarp fiber [PMF], and oil palm fronds [OPF]) in a fluidized bed reactor. Three kinetics schemes (simple, global, and advanced) were applied to pr...

The present work aims to optimize the operating conditions for biofuel production from fast pyrolysis of oil palm empty fruit bunch (OPEFB) biomass in a fluidized bed reactor. The coupled model of global reaction kinetics and heat transfer was applied to investigate the effects of operating conditions (reaction temperature in the range of 748–798 K...

This research aimed to study bioethanol production from Oil Palm Empty Fruit Bunches (OPEFB) with Simultaneous Saccharification and Fermentation (SSF) and Separate Hydrolysis and Fermentation (SHF) by Klyveromyces marxinus. The basic steps for bioethanol production from lignocellulosic biomass are (1) pretreatment for delignification, which is nece...

As the unknown values (X's) appear in the output response, a large amount of scan cells may not be observed during test. In this paper we present a flexible X-masking logic called selective X-masking to handle the majority of X's, while the X-tolerant compactor is applied to handle the remained X's. The objective of this approach is to improve the...

This paper presents a new parallel LFSR reseeding with selection register for mixed-mode BIST in order to reduce the number of test data. The dynamic seeds were injected in parallel form through the LFSR, phase shifter, and scan chains, respectively. The selection register was added to improve the efficiency of encoding test data. For seed computin...

In this paper, a novel parallel LFSR reseeding technique for mixed-mode BIST that is suitable and applicable to a multiple scan chain design. This approach can be applied to generate test cubes that detect Random Pattern Resistant (RPR) faults. A multiple test vector is used to guide the LFSR in order to generate target test cube at the application...

A mixed-mode built-in self-test (BIST) approach that deploys two new techniques is presented in this paper. Partial pattern matching allows the reduction of the number of patterns used for detecting random-pattern-resistant faults without relying on fault simulation. A multiple-control sequence is used to guide the linear feedback shift register (L...

This paper presents a novel approach to compacting a test response for a multiple scan chains design. The compactor design is based on extended an (n+1, k) BCH code, where k is the number of information bits and n+1 is the number of bits in the block. It can detect any odd number of single-bit errors and up to 2 t single-bit errors, where t is a po...

This paper presents a novel approach to compacting test response results for a multiple scan chains design. The compactors are based on (n+1, k) extended BCH code and guarantee detecting up to 2t single-bit errors and any odd number of single-bit errors, where n, k, t are integers depending on the particular BCH code used. Another technique uses co...

With core based design having been widely adopted, the use of BIST techniques has become more attractive testing approach. There are several techniques deployed to make BIST more efficient. Among these techniques mixed mode approach has proven to be more viable than earlier approaches. To minimize the control data required for such an approach, we...

This paper presents a novel approach to compact- ing a test response for a multiple scan chains de- sign. The compactor design is based on an extended (n + 1;k) BCH code, where k is the number of in- formation bits and n + 1 is the number of bits in the block. It can detect any odd number of single- bit errors or up to 2t single-bit errors, where t...