Suhani Malik

Suhani Malik
Sardar Vallabhbhai National Institute of Technology | SVNIT · Department Of Electronics Engineering

About

74
Publications
6,518
Reads
How we measure 'reads'
A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Learn more
7,203
Citations
Introduction

Publications

Publications (74)
Article
Full-text available
Disastrous effect of nickel on spinach was discussed by number of authors but the effect of amendments like biochar with nickel on Spinacea oleracea L. is not still discussed by any author of the world because biochar was used as soil amendments which play a vital role in reducing mobilization and uptake of nickel by spinach plants. As nickel conta...
Article
Full-text available
Dust accumulation capacity of Ficus carica L. and Psidium guajava L. was investigated from eight different sites of Multan, Pakistan. Leaves of both plants were used for analyzing biometric (leaf area, fresh and dry weights) and biochemical attributes (chlorophyll contents, carotenoids and ascorbic acid). Maximum dust accumulation was occurred in t...
Article
Full-text available
The biometric and biochemical attributes of alfalfa (Medicago sativa L.) seedlings were studied after their exposure to 0-120 mu M cadmium for 28 days using hydroponic culture. The growth, photosynthetic area and pigment contents (chlorophyll a, b and total) declined significantly (p <= 0.05) in the presence of high cadmium concentrations (90 and 1...
Article
Full-text available
Heavy metals toxicity in the human being is creating an alarming condition in the world. Not only are these metals largely effecting the growth of many plants but also the consumer’s health. In sector of agriculture for many years Pakistan is facing the reduction in availability of edible oil. The demand is fulfilled by importation by spending huge...
Article
Glenohumeral dislocations Key facts • Anterior shoulder dislocations are usually clinically obvious • Posterior shoulder dislocations can be difficult to identify • The shoulder is the most commonly dislocated joint in the body • 95% of shoulder dislocations will be anterior • Patients < 30 years of age have a high risk of recurrence Clinical prese...
Article
Objective: To assess the body weight, paired testicular weight and relative tissue weight index (RTWI) of male adult albino rats after the long and short term use of sildenafil citrate. Background: As very little attention has been given to explore the effects of a sildenafil citrate on histological aspects of testes, hence this experimental study...
Article
Objective: To determine the effects of Vitamin A excess on postnatal thymic development in albino rats. Study design: Experimental Place and Duration of Study: This study was conducted in the Department of Anatomy/ Histopathology, Shaikh Zayed Postgraduate Medical Institute, Lahore from September 2008 to September 2009. Materials and Methods: Study...
Article
Objective: To determine the teratogenicity of Vitamin A excess on intrauterine development of thymus in albino rats. Study Design: Experimental study Place and Duration of Study: This study was conducted at the Department of Anatomy/Histopathology, Shaikh Zayed Postgraduate Medical Institute, Lahore from September 2008 to September 2009. Materials...
Article
ChemInform is a weekly Abstracting Service, delivering concise information at a glance that was extracted from about 100 leading journals. To access a ChemInform Abstract of an article which was published elsewhere, please select a “Full Text” option. The original article is trackable via the “References” option.
Conference Paper
In multiprocessor based SoCs, optimizing the communication architecture is often as important, if not more important, than optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of architectures of processing elements, the same is not true for the communication architectures. This pa...
Conference Paper
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip communication. The tight delay requirements faced by on-chip networks have resulted in prior microarchitectures being largely performance-driven. While performance is...
Conference Paper
Given the growth in application-specific processors, there is a strong need for a retargetable modeling framework that is capable of accurately capturing complex processor behaviors and generating efficient simulators. We propose the operation state machine (OSM) computation model to serve as the foundation of such a modeling framework. The OSM mod...
Conference Paper
The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. While there are several mature methodologies for the modeling and ev...
Article
Full-text available
The Mescal project brings a formalized, disciplined methodology to the design of programmable platform-based systems, enabling the exploration of a wide array of architectures and a correct-by-construction path to implementation.
Article
Silicon capability has enabled the embedding of an entire system on a single silicon die. These devices are known as systems-on-a-chip. Currently, the design of these devices is undisciplined, expensive, and risky. One way of amortizing the cost and ameliorating this design risk is to make a single integrated circuit serve multiple applications, an...
Article
Full-text available
For humans, to view a scene with two eyes is clearly more advantageous than to do that with one eye. In computer vision however, most of high-level vision tasks, an example of which is face tracking, are still done with one camera only. This is due to the fact that, unlike in human brains, the relationship between the images observed by two arbitra...
Conference Paper
A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms - increasingly referred to as programmable platforms. For the platform manufacturer, programmabi...
Conference Paper
Full-text available
Interaction with virtual objects in an augmented environment enhances the user's interpretation of their presence. An augmented reality (AR) system that uses computer vision for registration can use the same technology for simple gesture recognition. This paper describes hand detection and simple gesture recognition techniques useful in pattern-bas...
Article
Full-text available
With the invention of fast USB interfaces and recent increase of computer power and decrease of camera cost, it has be- come very common to see a camera on top of a computer monitor. Vision-based games and interfaces however are still not common, even despite the realization of the benefits vision could bring: hand-free control, multiple-user inter...
Article
Full-text available
This paper presents our work in developing an application specific multiprocessor system for SAT, utilizing the most recent results such as the development of highly efficient sequential SAT algorithms, the emergence of commercial configurable processor cores and the rapid progress in IC manufacturing techniques. Based on an analysis of the basic S...
Conference Paper
This research examines the role of dynamically reconfigurable logic in systems-on-a-chip (SoC) design. Specifically we study the overhead of storing and downloading the configuration code bits for different parts of an application in a dynamically reconfigurable coprocessor environment. For SoC designs the different configuration bit-streams will l...
Conference Paper
Boolean satisfiability is probably the most studied of the combinatorial optimization/search problems. Significant effort has been devoted to trying to provide practical solutions to this problem for problem instances encountered in a range of applications in electronic design automation (EDA), as well as in artificial intelligence (AI). This study...
Conference Paper
Full-text available
This paper presents a novel approach for retargetable static software timing analysis. Specifically, we target the problem of determining bounds on the execution time of a program on modern processors, and solve this problem in a retargetable software development environment. We also describe the modeling of important features in contemporary archi...
Conference Paper
One of the most important features of current state-of-the-art SAT solvers is the use of conflict based backtracking and learning techniques. In this paper, we generalize various conflict driven learning strategies in terms of different partitioning schemes of the implication graph. We re-examine the learning techniques used in various SAT solvers...
Article
This paper presents a novel approach for retargetable static software timing analysis. Specifically, we target the problem of determining bounds on the execution time of a program on modern processors, and solve this problem in a retargetable software development environment. We also describe the modeling of important features in contemporary archi...
Article
This paper presents a new algorithm for exact estimation of the minimum memory size required by programs dealing with array computations. Based on parametric partitioning of the iteration space and formalized live variable analysis, our algorithm transforms the minimum memory size estimation into an equivalent problem: integer point counting for in...
Conference Paper
Full-text available
Comprehensive study of incremental algorithms and solutions in the context of CAD tool development is an open area of research with a great deal of potential. Incremental algorithms for synthesis and layout are needed when design undergoes local or incremental change. Often these local changes are made to react to local change in the design, correc...
Article
The issues of software compute time and complexity are very important in current computer-aided design (CAD) tools. As field-programmable gate array (FPGA) speeds and densities increase, the opportunity for effective hardware accelerators built from FPGA technology has opened up. This paper describes and evaluates a formula-specific method for impl...
Conference Paper
We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limited quantity of silicon to program ROM, so application software must be maximally dense. Additionally, the software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, curren...
Conference Paper
Dynamic power management is one of the most popular and successful low power design techniques in commercial integrated circuits, especially microprocessors. However, despite its significance, relatively little has been published about it. The purpose of this paper is to provide an open discussion of the application of dynamic power management for...
Conference Paper
Full-text available
This paper introduces the use of the Complete-1-Distinguishability (C-1-D) property for simplifying FSM verification. This property eliminates the need for a traversal of the product machine for the implementation and the specification. Instead, a much simpler check suffices. This check consists of first obtaining a 1-equivalence mapping between st...
Conference Paper
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instruction design which can guarantee minimum overhead for programs that make use of implicit indirect addressing. Second, we give a formulation and propose a solution for the prob...
Conference Paper
Full-text available
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer paths, that can be used for efficiently dismantling basic block DAGs (Directed Acyclic Graphs) into expression trees. This approach builds on recent results which report o...
Conference Paper
Full-text available
Software constitutes a major component of today's systems, and its role is projected to continue to grow. This motivates the need for analyzing power consumption from the point of view of software-something that circuit and gate level power analysis tools are inadequate for. This paper describes an alternative, measurement based instruction level p...
Article
Full-text available
We present a method for determining a tight bound on the worst case execution time of a program when running on a given hardware system with cache memory. Caches are used to improve the average memory performance, however, their presence complicates the worst case timing analysis. Any pessimistic predictions on cache hits/misses will result in loos...
Article
Embedded computer systems are characterized by the presence of one or more processors running application specific software. A large number of these systems must satisfy performance constraints in addition to cost constraints. Because embedded systems are constructed from large, complex components — CPUs and ASICs — we need new techniques to analyz...
Conference Paper
Full-text available
This paper addresses the problem of speeding up functional (delay-independent) logic simulation for synchronous digital systems. The problem needs very little new motivation-cycle-based functional simulation is the largest consumer of computing cycles in system design. Most existing simulators for this task can he classified as being either event d...
Conference Paper
Embedded systems generally interact with the outside world. Thus, some real-time constraints may be imposed on the system design. Verification of these constraints requires computing a tight upper bound on the worst case execution time (WCET) of a hardware/software system. The problem of bounding WCET is particularly difficult on modern processors,...
Conference Paper
Full-text available
An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions...
Conference Paper
Full-text available
This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,∞] model. Optimality is guaranteed by sufficient co...
Conference Paper
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Significant points of difference have been observed between this model and the ones developed earlier for some general-purpose commercial micr...
Conference Paper
Full-text available
IC designers are now increasingly concerned about the delay due to interconnection wires. In the past, these effects have been largely ignored during logic design-primarily due to their negligible contributions and also because of the difficulty of predicting the wiring resulting from the subsequent layout stage. In this paper, an estimation model...
Conference Paper
Full-text available
Recent years have witnessed a rapid growth in research activity targeted at reducing energy consumption in microprocessor based systems. However, this research has by and large not recognised the potential energy savings achievable through optimization of software running on the microprocessor. This paper presents an overview of techniques used in...
Article
Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provi...
Article
Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but the authors u...
Conference Paper
High performance circuit design is becoming increasingly important in VLSI design. The most important problem faced in the design of these circuits is to meet a certain performance level. In the past few years CAD algorithms and tools have been well developed that improve the performance of logic circuits in the sense that the worst case delay is m...
Conference Paper
The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the...
Conference Paper
The authors show how unmodified conventional Automatic Test Pattern Generators (ATPG) for such faults can be used for functional timing analysis without sacrificing computational efficiency in comparison with existing approaches to the same problem. This is a significant result since it permits use of the entire body of work in ATPG for this proble...
Conference Paper
The authors address the problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table. They give a procedure to extract the complete set of possible flow tables from...
Conference Paper
The problem of verifying that the gate-level implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table, under the fundamental mode of operation, is considered. A procedure for extracting the complete set...
Conference Paper
The authors develop efficient methods for computing an exact probability distribution of the delay of a combinational circuit, given probability distributions for the gate and wire delays. The derived distribution can give the probability that a combinational circuit will achieve a certain performance, across the possible range. The techniques targ...
Article
Reaction of the o-halonitrobenzenes (II) with the zinc salt (I) of 2-amino-4-trifluoromethylbenzenethiol gives the title compounds (III) via Smiles rearrangement.
Article
Full-text available
Vision-based registration techniques for augmented reality systems have been the subject of intensive research recently due to their potential to accurately align virtual objects with the real world. The downfall of these vision-based approaches, however, is their high computational cost and lack of robustness. This paper describes the implementati...

Network

Cited By