Sudipa Mandal

• Doctor of Philosophy
• PhD Student at Indian Institute of Technology Kharagpur

Mixed-signal assertions need to be monitored over dense time during analog simulation because analog events are not aligned with clock boundaries in general. On the other hand, simulation of large integrated circuits regularly employs clocked approximations to accelerate the simulation of the analog content in the design. Migrating the analog asser...

The design of the power management logic (PML) of complex low power system-on-chip (SoC) designs is rooted in the expected workload patterns in the target architecture. The increasing functionality of SoCs is complimented by increasingly diverse usage patterns among its users, leading to a situation where the same device is power efficient for some...

Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consi...

The ability to produce music is perhaps the most endearing quality in human beings. The sounds of music all over the world stand united on the 12 notes in an octave. While the physics of music and the incredible ability of human beings to perceive and reproduce notes and rhythm has been the subject of significant research spanning centuries, Indian...

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. The power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low...