Sudeb Dasgupta

Sudeb Dasgupta
Indian Institute of Technology Roorkee | University of Roorkee · Department of Electronics and Computer Engineering

Ph.D

About

161
Publications
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1,393
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Publications

Publications (161)
Article
A novel approach to overcome Boltzmann’s tyranny is to exploit the negative capacitance (NC) effect found naturally in many ferroelectric (FE) materials. We apply a set of coupled equations based on electrostatics, Kirchoff’s law, and a well-calibrated Ginzburg-Landau-Khalatnikov technology computer-aided design (TCAD) model to simulate an organic...
Chapter
This paper explores source/drain (S/D) spacer technology-based reconfigurable field-effect transistors (RFETs) and a detailed physical insight toward the advantages of using spacer oxide in RFETs for applications involving rapid temperature fluctuations and reduction of circuit delay in contrast to conventional ambipolar FETs and other devices base...
Article
In this paper, we have developed a physics-based compact model for surface potential and drain current for a dual gate source/drain (S/D) spacer-based silicon nanowire reconfigurable field-effect transistor (RFET). The models are derived by dividing the active region of the device into several portions based on positioning of the gates, spacers, an...
Article
Full-text available
This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-to-band tunneling (BTBT) for their on-current generation. I...
Article
A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of v...
Article
In this paper, we have developed an analytical model of double gate MOSFET using Green's function approach in the subthreshold regime of operation. The exact analytical solution to 2-D Poisson's equation by Green's function approach is redefined and Fourier coefficients are calculated correctly that has a direct impact on the outcomes of the model....
Article
As the gate lengths of FinFETs are scaled into nano meter regime, spatial variations in oxide thickness (Tox) and junction depth (Xj) of source/drain (S/D) doping profile will largely decide the performance of digital and analog circuits that can fall below or above the desired value. Of particular importance is operational transconductance amplifi...
Article
Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifi...
Article
For optimizing FinFET circuit-level parameters (such as number of fins) with performance predictability, it is necessary to understand the nature of voltage transitions at the nodes of a multistage logic circuit. Since the device's extension region parasitics are strong, these transitions need to be studied while considering them. We find using Tec...
Article
This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high-κ source-drain (S/D) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer (Lsp), gate dielectric and its t...
Conference Paper
Full-text available
In the past decade, high permittivity spacer materials has emerged as a potential performance booster in ultra scaled underlap devices to achieve better electrostatic control. However, the enhanced parasitic capacitance inherently associated with high-k materials poses several design challenges that limits its applicability to high-performance (HP)...
Conference Paper
Full-text available
Recently, junctionless transistor architectures with improved short channel characteristics have been extensively studied. JLTs, unlike inversion mode transistors (IMT), do not require precise control of doping profile in sub-20nm technology nodes. However, due to its highly doped channel, it faces several other challenges that limit its usage. To...
Conference Paper
Full-text available
High-ft spacer materials have been extensively researched for the suppression of short-channel effects (SCEs) in nano-scaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. The dynamic performance with enhanced device electrostatics can be effectively improved by du...
Article
An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is i...
Article
Full-text available
In this paper, we present a physics based semi-analytical model for channel potential of symmetric double gate tunnel field effect transistor (TFET). The analytical results are compared with TCAD Sentaurus simulated data. We have used a fitting parameter λ, which represents the screening length (or Debye length) of the device, in this work this fit...
Conference Paper
Inherent suppression of short channel effects, reduced sub-threshold and gate-dielectric leakage, good scalability and ease of integration in analog, digital and RF circuits makes SOI Fin FET an important device for mixed signal and system on chip (SoC) solutions. In this work we carry out the feasibility study of Fin FET transistor for analog to d...
Article
Full-text available
In this letter we optimize and investigate for the first time, the effect of Source/Drain (S/D) spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor (SiNWFET). Using extensive 3-D TCAD simulations we show that the OFF-state leakage can be reduced by more than 2 orders of magnitude owing to the combined u...
Conference Paper
Full-text available
High permittivity materials have considered as a key enabler in nano-scaled underlap devices to achieve better electrostatic control. However, the enhanced fringing capacitance inherently associated with high-k materials poses several design challenges that limits its usage in high-performance (HP) circuits applications. To simultaneously improve t...
Article
Full-text available
High-k spacer materials have been extensively studied nowadays for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance. Interestingly, this paper demonstrates effective reduct...
Conference Paper
Full-text available
In this work an attempt has been made to optimize the double gate underlap FinFET devices so as to approach the ITRS targets for the year 2015 for HP (High Performance) applications. Source/Drain doping engineering, gate dielectric engineering, spacer engineering and metal gate work function engineering have been explored for achieving optimal devi...
Article
A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The...
Article
Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm...
Article
Full-text available
During recent years, high-k spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects (SCEs) in nano-scaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using the...
Article
We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose...
Conference Paper
Full-text available
In this paper, we present the impact of spacer dielectric on a junctionless transistor (JLT) FinFET based circuit/SRAM memory cell. JLT FinFETs with high-k spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in the OFF-state...
Article
Full-text available
In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive...
Article
Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay model...
Article
The reliability of multigate metal-oxide-semiconductor (MOS) devices is an important issue for novel nanoscale complementary MOS (CMOS) technologies. We present an analytic degradation model of double-gate (DG) and gate-all-around (GAA) MOS field-effect transistors (MOSFETs) in the presence of localized interface charge. Furthermore, we consider th...
Conference Paper
Full-text available
This paper proposes a dual-k spacer FinFET architecture that shows superior electrostatic integrity over the conventional low-k spacer underlap device and thus suppress SCEs. Furthermore, the proposed dual-k structure explores the possibility of symmetric FinFETs that helps to augment all SRAM design metrics without affecting cell-ratio and pull-up...
Article
Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-ou...
Article
Full-text available
Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual-$k$ s...
Article
FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be...
Conference Paper
Full-text available
In nanowire CMOS design matching n-FET and p-FET current drive and threshold voltage for symmetric performance is a challenging problem. In this paper, we investigate different approaches to match the n- and p-FET drives in silicon nanowire (Si-NW) CMOS inverter. Device design parameters: gate length (LG), number of nanowire (NNW), wire diameter (D...
Article
As the MOSFET is scaled into a nanoscale regime, spreading of source/drain (S/D) dopant into the channel region will facilitate the lateral electric field spread into the channel and in turn deteriorate the gate electrostatic integrity. The short channel effects and performance are aggravated with the increase in lateral straggle (σL) of S/D Gaussi...
Article
Full-text available
This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventi...
Article
Full-text available
This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with...
Conference Paper
Full-text available
The undoped underlap region is unavoidable in devices with gate length 16nm or less to reduce SCEs. For the first time, this research paper addresses the complete underlap optimization analysis along with the spacer engineering from the device to circuit perspective. We elaborate the impact of underlap on drive current, leakage current and their ra...
Article
Full-text available
In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by...
Article
In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective...
Article
Among the multigate structures, FinFET is emerging as a promising candidate due to its better gate electrostatic control and ease of manufacturability. However, loss of gate electrostatic integrity (EI) is still observed in FinFET while it is scaled down to nano-scale regime, resulting in deterioration of analog performance. Most importantly, preci...
Article
In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are...
Conference Paper
FinFET devices with source drain underlaps are attractive due to their high Ion/Ioff ratios [1]. However, a thorough understanding of the device parasitics on underlap FinFET circuit performance is yet to be attained. In this paper, we report a new Extension Transistor Induced Capacitance Shielding (ETICS) phenomenon. Due to this phenomenon, the ef...
Article
Process variation is an important design concern in current nanoscale regime. This research paper analyzes the effect of process induced height and width variations for a multi-walled carbon nanotube (MWCNT) bundle interconnects. For different bundle heights and widths, the average deviation in crosstalk delay is analyzed for bundles having MWCNTs...
Article
This research paper presents different leakage mechanisms including the subthreshold and gate leakage current that occurs due to the aggressive scaling in nanoscale CMOS VLSI circuits. A novel algorithm is proposed based on the conventional gate replacement technique that is used to reduce the leakage current in CMOS VLSI circuits. This technique e...
Conference Paper
Full-text available
In this paper a TCAD method to determine surface electron density of a three terminal (3T) symmetric double gate silicon n-tunnel FET (DG Si nTFET) is presented. This research paper presents the changes in the channel surface electron density of symmetric n-Tunnel Field Effect Transistor (nTFET) devices. The physical reasoning behind the modeling a...
Conference Paper
Full-text available
This paper proposes an overall improvement in performance of Gate-Source/Drain underlap FinFET structure by introducing the concept of dual-k spacer between gate and source. By optimizing the underlap length, we demonstrate the sensitivity of dual-k spacer width. We analyze that the variation in width of high-k presents a noticeable improvements in...
Conference Paper
This research paper introduces a new modeling approach for different bundled CNT structures. Based on the arrangements of single- and multi-walled CNTs in bundle, two different structures of mixed CNT bundles (MCBs) are proposed. Performance in terms of propagation delay is compared between different bundled CNT structures by using a driver-interco...
Conference Paper
Low power devices promote the development of micro power generators (MPGs). There is an increasing interest in harvesting ambient vibration energy through piezoelectric means by which one can potentially draw 10-100's of μW of available power. The limitations of existing piezoelectric harvesters is in their interface circuitry consuming large power...
Conference Paper
In this work we present a simulation based study of the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive current of narrow width devices significantly depend upon the actual width of a device. We present a model for estimating width dependen...
Conference Paper
In recent years, leakage power dominates the dynamic power in nanoscale CMOS VLSI circuits. This research paper describes different leakage mechanisms that includes subthreshold and gate leakage current. A novel approach of reduction in leakage current is proposed which is primarily based on the conventional gate replacement technique. This approac...
Conference Paper
Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution over Cu or other materials used in global VLSI interconnects. Initially, this research paper proposes an equivalent single conductor (ESC) of MWCNT which is well accurate to a multiple transmission line RLC network with an average error of 1.67% or below. Fin...
Article
Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and to...
Article
Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a refer...
Conference Paper
This paper investigates the stress liner induced performance enhancement in multi-fingered devices. It is observed that the liner induced stress is not uniform in all the fingers and fingers located at the edges of multifingered devices have larger channel stress. As a result there is an unaccounted change in the drive current of fingers, sharing a...
Article
In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D...
Article
We present a novel approach for matching the drive current of n-FET with p-FET in CMOS logic circuits through source-drain extension profile tuning. Our approach overcomes the current quantization issue in nanowire/FinFET devices. We show that, in comparison to conventionally used method, where the width of p- device is increased to match the drive...
Article
In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to...
Article
In this study, the authors evaluate different schemes of address decoders based on bulk, single gate (SG) silicon-on-insulator (SOI) and double gate (DG) FinFET technology. Schemes differ in terms of back gate connections, and swing on the enable and address lines. The analysis for delay, power dissipation and critical charge has been carried out....
Conference Paper
In this work we studied the impacts of number of fingers in strain engineered MFGSs on the circuit performance designed using multi-finger gate structures (MFGSs) for three different layout scenarios. We studied the stress induced in the channel of MFGSs by decoupling different stress sources and dependence of channel stress on the layout of gate s...
Conference Paper
In this paper we have analysed the analog performance of conventional as well as dual-k spacer based underlap FinFET. Dual-k spacer in underlap FinFET is used to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out of gate sidewall fringing fields, thereby, increasing transconductance and reducing output c...