Stephen Trimberger

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than si...

Programmable logic devices permit a new way to practice yield improvement: redundancy at configuration time. By doing so, the authors avoid the overheads of traditional redundancy: explicit spares, replacement logic and on-chip non-volatile memory. This presentation describes a method for avoiding defects that also does not require a unique place-a...

A method, non-transitory computer readable medium, and apparatus for preventing accelerated aging of a physically unclonable function (PUF) circuit are disclosed. For example, the method monitors an environmental condition associated with the physically unclonable function circuit, detects a change in the environmental condition associated with the...

A method and system of preventing data imprinting. The data includes a payload and a token that may be stored in a memory. The token provides information about the payload format and determines how that payload may be interpreted. The data field may be corrected and read into a device or may be converted and then written back to the memory.

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than si...

A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentica...

A method of enabling detection of tampering with data provided to a programmable integrated circuit is described. The method comprises modifying a portion of the data to establish randomness in the data; and inserting, by a computer, a redundancy check value in the portion, wherein the redundancy check value is based upon the modified portion of th...

A circuit for detecting power analysis attacks includes at least one load circuit, a power supply line, and a switch coupled to the load circuit and to the power supply line. The switch is configured to enable and disable the at least one load circuit, and a voltage monitor is configured to sample voltage levels of the supply voltage. A detection c...

An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensi...

Since their inception, field-programmable gate arrays (FPGAs) have grown in capacity and complexity so that now FPGAs include millions of gates of logic, megabytes of memory, high-speed transceivers, analog interfaces, and whole multicore processors. Applications running in the FPGA include communications infrastructure, digital cinema, sensitive d...

FPGA devices provide a range of security features which can provide powerful security capabilities. This paper describes many security features included in present-day FPGAs including bitstream authenticated encryption, configuration scrubbing, voltage and temperature sensors and JTAG-intercept. The paper explains the role of these features in prov...

An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit...

form only given. Moore's Law continues, but for how long? Many are predicting the end, or at least the slowing, of semiconductor scaling even as FinFETs are being introduced. New technologies, such as 3D integration, offer new opportunities for silicon vendors and customers. These technology trends are converging on Programmable Logic. FPGA vendors...

In one embodiment, a circuit arrangement for performing cryptographic operations is provided. The circuit includes a substitution block, a cryptographic circuit coupled to the substitution block, and a balancing circuit coupled to the substitution block. The substitution block includes a memory unit storing substitution values and ones-complement v...

A programmable interconnect element for an integrated circuit device is described. The programmable interconnect comprises a first selection circuit coupled to a plurality of input lines and having a first output; a register having a first input coupled to the first output; and a second selection circuit enabling the selection of a value at the fir...

In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is track...

A method of correcting adjacent bit errors in a memory is disclosed. The method comprises determining that there are errors in each set of two non-overlapping sets of the memory; changing a stored value of a memory cell of the memory until it is determined that a single error exists in the memory; identifying a location of the single error in the m...

In one embodiment, a method is provided for analyzing a circuit design. For each sub-circuit of a plurality of sub-circuits specified in the circuit design, a logic level probability is determined for each output of the sub-circuit. The logic level probability indicates the probability that an output of the sub-circuit will have a first value in re...

A multiplexer-based network provides the routing equivalent to a non-blocking crossbar network having a plurality of crossbar switches making up an ingress, middle, and egress stages. The non-blocking crossbar network includes crossbar rows, each including outbound and inbound internal connections to another crossbar row. The multiplexer-based netw...

In one aspect, a method for providing encrypted information includes encrypting a true message to form an encrypted true message. A ciphertext message including the encrypted true message is formed, where multiple messages are decryptable from the ciphertext message. The messages include a true message including true information and at least one de...

A method of using an integrated circuit (IC) can include reading a device code from a selected IC, calculating a measure of randomness from a plurality of values specified within the device code, and comparing the measure of randomness to a randomness criterion. A determination can be made as to whether the selected IC is compromised according to t...

A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a...

An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fi...

An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An error correction code may be employed to correct an error in the value of the reproduc...

Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic patterns that hardware components of the target device can implement. Unused hardware...

An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided...

A method and system of detecting data imprinting in a memory is described. Data having known bit values is stored in a location in the memory and the data is read to determine the amount of the known bit values that can be successfully read after an attempt to erase the data. The amount of data that can be successfully read is compare to a threshol...

A security circuit for a reprogrammable logic IC includes an evolved circuit that ties the performance of the security circuit to the physical properties of that particular reprogrammable logic IC. The security circuit can be a decryption and/or encryption circuit that decrypts and/or encrypts, respectively, a configuration bitstream for the IC. Be...

FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use...

FPGA bitstream encryption blocks theft of the design in the FPGA bitstream by preventing unauthorized copy and reverse engineering. By itself, encryption does not protect against tampering with the bitstream, so without additional capabilities, bitstream encryption cannot prevent the FPGA from executing an unauthorized bitstream. An unauthorized bi...

The paper presents the birth of the world first FPGA, called the XC2064. Xilinx and Seiko worked together to solve the whisker issue and a few others, and soon the XC2064, the world's first FPGA, was commercially available. It was the beginning of a fruitful relationship between the two companies. In addition to providing an additional revenue stre...

Although innovations in manufacturing technology help in reducing variations, IC design variations are a fact of life. In addition to random variations, systematic stress induced variations are becoming increasingly important. This panel will bring the diverse views from academia, foundries, fabless and IDM communities to address various topics on...

This study presents a method for implementing a circuit in a field programmable gate array (FPGA) that protects the circuit from the effects of single-event upsets (SEUs). When routing nodes within the circuit using the interconnect lines of the FPGA, two routed nodes are separated from each other by at least two programmable interconnect points (P...

This paper presents a model of interstellar communication that separates transmission, formatting, syntactic and semantic aspects. The seven-level model includes a level for the physical transmission medium, the encoding of data in that medium, the format of the encoded data, the symbols of the message, the structure of the message, the interpretat...

Small gates, such as AND2, XOR2, and MUX2, have been mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small...

This special issue on Security in Reconfigurable Systems Design reports on recent research results in the design and implementation of trustworthy reconfigurable systems. Five articles cover topics including power-efficient implementation of public-key cryptography, side-channel analysis of electromagnetic radiation, side-channel resistant design,...

Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the. programmable logic block (PLB) to reduce area and power and increase performance in FP-GAs. However, it is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a sm...

As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded. FPGA manufacturers have added security features to protect designs from unauthorized copy,...

FPGAs are increasingly used in military applications, the security of a design when the part is powered off is an important property that needs to be analyzed. In this paper, we study data remanence in modern FPGAs using a custom 90nm FPGA designed for this test. The effects of temperatures, architecture, memory topology, and power off methods are...

Summary form only given. Over the past twenty years, FPGAs evolved from simple glue-logic chips to complex systems-on-a-chip. This change can be viewed having distinct phases, each with different architecture, tools and methodology requirements. Are we now facing another phase change? Will FPGAs continue to evolve incrementally or are we about to s...

Using FPGAs, a designer can separate the design process from the manufacturing flow. Therefore, the owner of a sensitive design need not expose the design to possible theft and tampering during its manufacture, dramatically simplifying the process of assuring trust in that design. Modern FPGAs include bitstream security features that turn the field...

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and imple...

In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is hi...

In this paper a die stacking technology, leveraging on through die via (TDV) integration and wafer bonding, is presented. Using state-of-the-art volume manufacturing environment, 10:1 aspect ratio TDV and wafer-level bonding technology are developed and initial electrical and reliability characterization results of TDVs are provided. The opportunit...

Programmable logic devices such as FPGAs are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than ASICs and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered ap...

The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon mainstream. Major ASIC vendors have responded by reviving masterslice gate arrays, standard prefab die with design-specific metal layers. They claim lower NREs, quicker delivery and easier design than cell-based ASICs, and lower unit cost, better speed, cap...

In this paper we discuss new techniques for timing-driven placement and adaptive delay computation for hierarchical PLD architectures.Our algorithm follows the natural recursive k-way partitioning-based approach to placement on such devices. Our contributions ...

Summary The future of network security depends on encryption provided in the crucial building blocks, like switches, routers, bridges, and other communication equipment. All broadband applications need high-speed cryptosystems to speed up high-bandwidth data transfers and to protect privacy. DES cryptographic hardware is used to protect civilian sa...

This paper describes two implementations of a Data Encryption Standard (DES) encryptor/decryptor that operate at data rates up to 12 Gbps. The 12 Gpbs number is faster than any previously published design. In these DES implementations, the key can be changed and the core switched from encryption to decryption mode on a cycle-by-cycle basis with no...

The ability to reconfigure around manufacturing defects and operational faults increases FPGA chip yield, reduces system downtime and maintenance in field operation, and increases reliabilities of mission- and life-critical systems. The fault reconfiguration technique discussed in this work use the principle of node covering in which reconfiguratio...

An algorithm is presented for partitioning a design in time. The algorithm devides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed in the FPGA to emulate the large design. The tool includes facilities for optimizing the partitioning to improve routability, for fitt...

This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded f...

High-capacity FPGAs pose device architects with a variety of problems.The most obvious of theseproblems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture.

Although many traditional Mask Programmed Gate Array (MPGA) algorithms can be applied to FPGA routing, FPGA architectures impose critical constraints and provide alternative views of the routing problem that allow innovative new algorithms to be applied. This paper describes routing models provided by some commercial FPGA architectures, and points...

Since their introduction in 1985, Field Programmable Gate Arrays (FPGAs) have become a preferred medium for implementing digital logic designs. The increased popularity of FPGAs results from significantly increased capability of FPGAs. This paper discusses the progress of FPGA technology in three areas: manufacturing process, architecture and softw...

Preface. 1: Introduction. 1.1. Logic Implementation Options. 1.2. What is an FPGA? 1.3. Advantages of FPGAs. 1.4. Disadvantages of FPGAs. 1.5. Technology Trends. 1.6. Designing for FPGAs. 1.7. Outline of Subsequent Chapters. 1.8. References. 2: SRAM Programmable FPGAs. 2.1. Introduction. 2.2. Programming Technology. 2.3. Device Architecture. 2.4. S...

Since their introduction, SRAM-programmable FPGAs have become very popular. Carter [1986], Hsieh [1987, 1990], Kean [1989], Furtek [1990], Hastie [1990], Kawana [1990], Muroga [1991], Ebeling [1991], Chow [1991], Hauck [1992], Hill and Britton [Hill 1992][Britton 1993] and Cliff [1993] have all proposed SRAM-programmable FPGAs.

A field-programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by writing into on-chip static memory is described. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. Reprogrammable technolo...

Lookup-table-based field-programmable gate array (FPGA) logic blocks contain multiple lookup-tables, flip flops, and other features. The partitioning of this logic into physical blocks has a logical component, traditionally handled as part of technology mapping in logic synthesis, and a physical component, traditionally handled by placement in phys...

A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm, DAG-Map, carries out technology mapping and delay optimization on the entire Boolean network, ...

The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade

A datapath must be built that supports the instruction set and control requirements. Although many datapaths are built using standard bit-slice parts, like the 2901, such a standard part cannot be used because an extra adder for incrementing the program counter, a pipeline of instruction registers and a memory address register are all needed. Altho...

A Silicon Compiler is a CAD program that translates a high-level description of complex circuits into the artwork needed to fabricate a semiconductor integrated circuit chip. The high-level description used depends on the function to be built and on the capabilities of the silicon compiler. Three main types of silicon compilers are introduced, and...

So far, we have concentrated on tools for synthesis — tools that create layout. We now consider analysis tools, tools that check that the layout is correct. This chapter describes two tools for verification of layouts: a design rule checker (DRC) and a circuit extractor. A design rule checker checks that the widths, spacings and overlaps of feature...

This chapter is a review of the subset of interactive graphics programming techniques we need to build graphical CAD software. A full treatment of interactive graphics is beyond the scope of this book, but you can find it in Newman and Sproull (1979) and Foley and Van Dam (1982). Some familiarity with interactive graphics techniques and terminology...

Although many tools have been written to simplify and automate integrated circuit layout, the layout editor is still the workhorse of integrated circuit synthesis. A layout editor allows a user to specify graphically the shapes that make up his chip. The concepts involved are simple and powerful — a user draws what he wants to see on the chip. He n...

An integrated circuit designer uses simulation for two tasks, to verify that the design he made is actually what he wanted to make and to determine the operating speed of the resulting circuit. The same simulator may be used two different ways: interactively, for initial debugging of a circuit; and batch-like, to exhaustively verify the circuit. So...

There are two parts to reading a data file: processing the characters and building the results into a data structure. The former is commonly called syntax analysis and the latter semantic analysis. Since the data structures we wish to build may differ with every tool, we separate the two jobs. A parser is the tool that processes characters in an in...

A layout language is the most versatile and ultimately the most powerful layout tool a designer can have. It gives a designer the power of a programming language to specify a chip. Many layout tasks that would otherwise require tedious placement and checking in a layout editor can be done quickly with a program. A layout language is easy to impleme...

A layout generator, sometimes called a cell compiler, is a program that generates layout for a function using a predefined structure. The range of software that falls into this definition of layout generator is very large, encompassing everything from the parameterized inverter in Chapter 6 to placement and routing. We take a bottom-up approach to...

Plotting an integrated circuit design serves a dual purpose. First, it is a means for documenting a design. A hardcopy plot of the layout implicitly carries with it all the information about the design. Secondly, plotting is the time-honored method of verifying the correctness of a design. As a representation of the manufactured product, it is a pr...

We begin our investigation of design tools with a short discussion of integrated circuit design and the design process. We discuss the kinds of data that users manipulate and the tools they need during the design process.

The last decade has seen an explosion in integrated circuit technology. Improved manufacturing processes have led to ever smaller device sizes. Chips with over a hundred thousand transistors have become common and performance has improved dramatically. Alongside this explosion in manufacturing technology has been a much-less-heralded explosion of d...

VTIcompose is a graphical chip assembly tool. It is designed to ease the assembly of large-scale custom chips in a hierarchical manner, leaving the detailed cell design to other tools in the system. VTIcompose supports both manual and automatic placement and interconnection, with commands and data structures applicable to both exact placement and s...

The role of VLSI in the development of next-generation computers is examined. Progress in VLSI design aids and fabrication technology is discussed. Present capabilities are only a factor of between two and ten away from those required for the million-transistor chip.

The complexity of integrated circuits requires a hierarchical design methodology that allows the user to divide the problem into pieces, design each piece independently, and assemble the pieces into the complete system. The design herarchy brings out composition problems, problems that are a property of the assembly as a whole, not of one single in...

In large-scale integrated circuit design, chip assembly is more difficult, more time consuming. and more error prone than the design of the low-level cells. Assembly errors tend to persist until late in the design cycle requiring extensive rework. Unfortunately, the tools traditionally provided for custom integrated circuit design address the probl...

Errors in the chip assembly process are harder to find than errors in cell design, since they belong to no specific part of the design, but rather to the assembly as a whole. Assembly errors are more costly than call design errors also, since they often go unnoticed until late in the design cycle. Interactive graphic tools typically require that as...

Discusses how new computer-based layout systems are being used more and more to design LSIs. The new systems are faster than human designers and produce systems almost as good at reduced cost. Four basic methods in use are described.

The paper reviews the four basic ways to automate the layout for LSI and VLSI designs. These are standard cell, gate array, programmed logic array and standard floor plan. Advantages of gate arrays are discussed. Refs.

This paper discusses Pl.A designs in three MOS technologies: NMOS, CMOS/SOS and CMOS-Bulk. The purpose of this paper is not to introduce a new and exciting PLA design, nor is it to recommend one fabrication technology over another. Its purpose is to use PLAs as a standard, hopefully familiar layout strategy so that new designers can get a better un...

The problems encountered designing very large scale integrated circuits (VLSI) are fundamentally different from the problems encountered in the design of small scale integrated circuits. The differences require a new methodology of design for the new large scale circuits, and the new design methodology requires a new set of tools. The computer-aide...

Layout languages provide users with the capability to algorithmically define cells. But the specification language is so non-intuitive that it is impossible to debug a design in that language, one must plot it. Interactive graphics systems, on the other hand, allow the user to debug in the form in which he sees the design, but severely restrict the...

This is version 1.0 of the Sticks Standard. Software has been written to interface this standard to plotters, a graphic Sticks editor, a Stick compactor and several simulators. The Standard appears adequate to describe cells for chip assemblers as well as Stick diagram editing and compaction systems. However, this version of the Sticks Standard can...