Stefan Damjancevic- TUD Dresden University of Technology
Stefan Damjancevic
- TUD Dresden University of Technology
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11
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Publications (11)
To enable the low-cost design of 5 G IoT Standard reduced capability (NR-REDCAP) devices, hardware-software trade-offs must be made for various signal processing baseband kernels. Dedicated hardware for a kernel provides higher speed and power efficiency but limits the device’s programmability. With the varying range of user equipment (UE) deployme...
To enable the low-cost design of 5G IoT Standard reduced capability (NR-REDCAP) devices, hardware-software trade-offs must be made for various signal processing baseband kernels. Dedicated hardware for a kernel provides better speed and power efficiency but limits the device’s programmability. With the varying range of user equipment (UE) deploymen...
Les systèmes multiprocesseurs sur puce (MPSoC) sont des composants clés pour les applications complexes qui impliquent une grande pression sur la mémoire, les dispositifs de communication et les unités de calcul. Depuis vingt ans, MPSoC rassemble, lors d’un forum interdisciplinaire, des experts des systèmes matériels, des logiciels multicoeurs et d...
The new 5G Reduced Capability (RedCap) protocol offers up to 88x and 528x higher data rates and dynamic pilot placements compared to previous Cat-M and NB-IoT standards, respectively. This leads to high application variability of IoT devices and therefore poses a challenge for the implementation of channel estimation (CE), especially under weak rad...
Over the past few decades, we have seen rapid innovation in wireless communications. In this chapter, the authors give the reader a background on the 6G candidate waveform modulation generalised frequency division multiplexing (GFDM), develop a GFDM‐associated dataflow processing graph and pseudo‐code. To bridge the gap between workloads and hardwa...
As we target implementations of very high-end () specifications and look towards the future, it becomes apparent that the stringent execution deadlines in
physical layer
(PHY) procedures are hard to satisfy using traditional algorithms optimised for high throughput. Hence, if the designer adheres to the same throughput efficient algorithm and sim...
