Soon-Kyun Shin

Soon-Kyun Shin
Maxim Integrated | MAXIMINTEGRATED

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10
Publications
2,520
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185
Citations

Publications

Publications (10)
Article
Full-text available
A 12 bit 200 MS/s analog-to-digital converter (ADC) applies techniques of zero-crossing-based circuits as a replacement for high-gain high-speed op-amps. High accuracy in the residue amplifier is achieved by using a coarse phase in ZCBC followed by a level-shifting capacitor for fine phase. Sub-ADC flash comparators are strobed immediately after th...
Conference Paper
Pipeline ADCs have traditionally served as a general-purpose architecture for high-speed and high-resolution applications such as medical and wireless receivers. Recently, achieving the highest levels of linearity with ultra-low power consumption has proven to be extremely challenging using modern CMOS technology with limited headroom. While zero-c...
Article
Full-text available
This paper presents a CMOS power amplifier (PA) system designed with the explicit goal of customizing a high-output power transmitter for sensor applications, where the supply voltage from an energy storage element is often time varying. The PA is intended for use in a long-range sensor transceiver and can operate directly off a super-capacitor sou...
Conference Paper
Full-text available
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFD...
Conference Paper
A fully-differential zero-crossing-based 10b 26 MS/s pipelined ADC in a 65 nm CMOS process is presented. Switched-capacitor overshoot correction is compatible with the differential topology and allows faster operation. A CMFB is engaged in the coarse phase for constant common-mode. The 0.33 mm<sup>2</sup> ADC achieves 54.3 dB SNDR with a FOM of 161...
Article
A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow its transition time independent of process, voltage, temperature and output load variations. The prop...
Conference Paper
A slew rate-controlled output driver using capacitive feedback is described in this paper. To make a constant transition time in the output driver, a constant current source is used with capacitive feedback between output and the gate of output driver. The capacitor feedback path gives a current path which connects the gate of the output driver wit...
Conference Paper
This paper proposes a charge pump having a high driving capability for driving more than a load of 8 mA with a 5 V regulated output voltage. The output of the charge pump generates 5 V without any damages to the oxide using protection circuits, even though it uses 3 V MOS transistors. The prototype chip designed using 0.13 μm CMOS process provides...
Conference Paper
A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To...
Article
A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 CMOS process for storage device interface. PhaseLocked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To gene...

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