Sidharta Andalam

Sidharta Andalam
University of Auckland · Department of Electrical & Computer Engineering

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41
Publications
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390
Citations

Publications

Publications (41)
Preprint
The recent advancement of information and communication technology makes digitalisation of an entire manufacturing shop-floor possible where physical processes are tightly intertwined with their cyber counterparts. This led to an emergence of a concept of digital twin, which is a realistic virtual copy of a physical object. Digital twin will be the...
Preprint
Industrial cyber-infrastructure is normally a multilayered architecture. The purpose of the layered architecture is to hide complexity and allow independent evolution of the layers. In this paper, we argue that this traditional strict layering results in poor transparency across layers affecting the ability to significantly improve resiliency. We p...
Preprint
As the industrial cyber-infrastructure become increasingly important to realise the objectives of Industry~4.0, the consequence of disruption due to internal or external faults become increasingly severe. Thus there is a need for a resilient infrastructure. In this paper, we propose a contract-based methodology where components across layers of the...
Preprint
This demonstration presents a framework for building a resilient Cyber-Physical Systems (CPS) cyber-infrastructure through the use of hierarchical parametric assume-guarantee contracts. A Fischertechnik Sorting Line with Color Detection training model is used to showcase our framework.
Preprint
Full-text available
Digital twin is a virtual replica of a real-world object that lives simultaneously with its physical counterpart. Since its first introduction in 2003 by Grieves, digital twin has gained momentum in a wide range of applications such as industrial manufacturing, automotive and artificial intelligence. However, many digital-twin-related approaches, f...
Chapter
The recent advancement of information and communication technology makes digitalisation of an entire manufacturing shop-floor possible where physical processes are tightly intertwined with their cyber counterparts. This led to an emergence of a concept of digital twin, which is a realistic virtual copy of a physical object. Digital twin will be the...
Conference Paper
This demonstration presents a framework for building a resilient Cyber-Physical Systems (CPS) cyber-infrastructure through the use of hierarchical parametric assume-guarantee contracts. A Fischertechnik Sorting Line with Color Detection training model is used to showcase our framework.
Article
As the industrial cyber-infrastructure become increasingly important to realise the objectives of Industry 4.0, the consequence of disruption due to internal or external faults become increasingly severe. Thus there is a need for a resilient infrastructure. In this paper, we propose a contractbased methodology where components across layers of the...
Article
Full-text available
Models of the cardiac conduction system are usually at two extremes: (1) high fidelity models with excellent precision but lacking a real-time response for emulation (hardware in the loop simulation); or (2) models amenable for emulation, but that do not exhibit appropriate dynamic response, which is necessary for arrhythmia susceptibility. We intr...
Article
Full-text available
Hybrid systems combine discrete controllers with adjoining physical processes. While many approaches exist for simulating hybrid systems, there are few approaches for their emulation, especially when the actual physical plant is not available. This paper develops the first formal framework for emulation along with a new compiler that enables large-...
Article
Full-text available
Objective: A flexible, efficient and verifiable pacemaker cell model is essential to the design of real-time virtual hearts that can be used for closed-loop validation of cardiac devices. A new parametric model of pacemaker action potential is developed to address this need. Methods: The action potential phases are modeled using hybrid automaton...
Article
Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integ...
Article
Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integ...
Conference Paper
Virtual heart models have been proposed for closed loop validation of safety-critical embedded medical devices, such as pacemakers. These models must react in real-time to off-the-shelf medical devices. Real-time performance can be obtained by implementing models in computer hardware, and methods of compiling classes of Hybrid Automata (HA) onto FP...
Conference Paper
A cardiac model of networked Hybrid Automata (HA) cells or nodes is potentially very useful for industry validation of pacemaker algorithms. Such a model replicates the electrical conduction system of the heart and the interaction with a pacemaker. The benchmark is a network of more than 100 HAs. It exhibits several key phenomena that are typical f...
Article
Full-text available
The heart is a vital organ that relies on the orchestrated propagation of electrical stimuli to coordinate each heartbeat. Abnormalities in the heart’s electrical behaviour can be managed with a cardiac pacemaker. Recently, the closed-loop testing of pacemakers with an emulation (real-time simulation) of the heart has been proposed. This enables de...
Article
Full-text available
Hybrid systems are discrete controllers that are used for controlling a physical process (plant) exhibiting continuous dynamics. A hybrid automata (HA) is a well known and widely used formal model for the specification of such systems. While many methods exist for simulating hybrid automata, there are no known approaches for the automatic code gene...
Article
Full-text available
Safety-critical embedded systems, commonly found in automotive, space, and health-care, are highly reactive and concurrent. Their most important characteristics are that they require both functional and timing correctness. C has been the language of choice for programming such systems. However, C lacks many features that can make the design process...
Article
Automotive Electrical/Electronic (E/E)-architectures consist of various components which are generally developed independently. Due to the increasing size and complexity, component integration is highly challenging and already slight modifications to components or subsystems often require expensive re-testing and re-validation. As a remedy, we prop...
Conference Paper
Synchronous programs have been widely used in the design of safety critical systems such as the flight control of Airbus A-380. To validate the implementations of synchronous programs, it is necessary to map the program's logical time (measured in logical ticks) to physical time (the execution time on a given processor). The static computation of t...
Conference Paper
There has been a great deal of impetus for the design of predictable memory such as scratchpad memory. Moreover, static analysis of cache memory is an area of intense research activity. However, there has been minimal development of caches or scratchpads (SPMs) that can exploit the inherent concurrency in synchronous languages. In this paper, we ha...
Conference Paper
Full-text available
Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which complicates the Worst Case Execution Time (WCET) analysis problem. Existing approaches that precisely...
Conference Paper
Full-text available
This paper gives an overview of the system architecture and software design challenges for Electric Vehicles (EVs). First, we introduce the EV-specific components and their control, considering the battery, electric motor, and electric powertrain. Moreover, technologies that will help to advance safety and energy efficiency of EVs such as drive-by-...
Article
Full-text available
Safety critical real-time applications in aviation, automotive and industrial automation have to guarantee not only the functionality, but also the timeliness of the results. Here, a deadline is associated with the software tasks, and a failure to complete prior to this deadline could lead to a catastrophic consequences. Hence, for the correctness...
Conference Paper
Full-text available
Synchronous programs execute in discrete instants, called ticks. For real-time implementations, it is important to statically determine the worst case tick length, also known as the worst case reaction time (WCRT). While there is a considerable body of work on the timing analysis of procedural programs, such analysis for synchronous programs has re...
Conference Paper
Full-text available
Static timing analysis of a hard real-time application is necessary to ensure that task-level timing deadlines are always met. In many cases, it is preferable to include details about the operating environment to ensure precise timing analysis. However, adding an environment model increases the overall state space being analyzed, which can result i...
Conference Paper
Full-text available
We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multi-threading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory communications between concurrent threads that is guar...
Conference Paper
Full-text available
The IEC 61499 is an international standard for describing industrial process-control systems. Such systems typically consist of embedded computers that interact closely with physical processes within a feedback loop. In order to correctly control these physical processes, computations in response to inputs need to be done in a timely manner. A prog...
Conference Paper
Full-text available
We present a new language called Precision Timed C, for predictable and lightweight multithreading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory communications between concurrent threads, which is guaranteed t...
Article
Full-text available
Esterel programs have traditionally been compiled to software code for general purpose processors or to hardware netlists. This paper, instead, proposes a reactive processor for the direct execution of Esterel. This intermediate approach offers the same flexibility as software compilation, while at the same time, providing much better code size and...
Article
Full-text available
We propose a fully pipelined, multithreaded, reac- tive processor called STARPro for direct execution of Esterel. STARPro provides native support for Esterel threads and their scheduling. In addition, it also natively supports Esterel's pre- emption constructs, instructions for signal manipulation, and a notion of logical ticks for synchronous exec...
Conference Paper
Full-text available
Accurate estimation of the tick length of a synchronous pro- gram is essential for e!cient and predictable implementa- tions that are devoid of timing faults. The techniques to de- termine the tick length statically are classified as worst case reaction time (WCRT) analysis. While a plethora of tech- niques exist for worst case execution time (WCET...
Article
Full-text available
Precision Timed Architectures (PRET) are a recent proposal for designing processors for real-time embedded systems. These processors must guarantee precise worst case reaction time (WCRT) of applications without sacrificing throughput, and must allow the WCRT of programs to be computed simply as well as efficiently. The ob jective of this paper is to...
Article
Full-text available
The idea of predictable architectures has recently obtained more attention with the concept of a Precision Timed Machine (PRET) (5). The two goals are to guarantee precise timing without sacrificing throughput, and to simplify the worst case timing analysis of code executing on PRET machines. Such a PRET machine, based on the SPARC ISA, has been de...

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