Shinji Nishimura

• Hitachi, Ltd.

A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that i...

A compact 4 25-Gbps optical transceiver for short-reach communications using optical interconnects was developed. Its total power consumption is 2.2 W. A transmission experiment with the transceiver was successfully conducted at 25-Gbps data rate.

A novel 400-Gb/s (100-Gb/s × 4) physical-layer architecture for the next-generation Ethernet - using 100-Gb/s serial (optical single-wavelength) transmission - is proposed. As for the next-generation 400-Gb/s Ethernet, additional requirements from the market, such as power reduction and further miniaturization in addition to attaining even higher t...

A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variation...

We have developed a high-throughput, compact network switch (the RHiNET-2/SW) for a distributed parallel computing system. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are integrated on a compact circuit board. To realize high-throughput (64 Gbit/s) and low-latency network, the SW-LSI has a customized...

A compact 4 × 25 Gbps optical transceiver has been fabricated for an optical backplane system, which consists of a 4 × 25 Gbps DFB-LD array, a 4 × 25 Gbps PIN-PD array, and a CMOS transceiver chip. These are directly mounted on 9 × 14 mm² multi-layer ceramic package with an electromagnetic shield structure to suppress inner-channel crosstalk effect...

The first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-Gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer - was developed. Its power dissipation is 75% lower than that of a conventional SiGe-based gearbox LSI. To develop this low-power gearbox LSI, the power dissipation of its 25-Gb/s interface...

The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that...

Photonic technology is an important solution to achieve power-saving routers/switches for green networks. As networking is a worldwide matter, and as the power consumed by routers and switches is rapidly increasing, power-efficient green networks have become a subject of great interest. The main issue of green networking is relieving the increasing...

Electric power consumed by routers and switches is rapidly increasing with expanding flow of information. To suppress the increasing power consumption, optics has been expected to play an important role for interconnects of such network equipments. We describe the advanced optical interconnecting technologies: highly-efficient optical devices and e...

The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a "gearbox" LSI-which switches between 10x10Gb/s data signals on the physical-coding-sublayer side and 4x25Gb/s data signals on the physical-media-dependent side. A gearbox LSI based on 0.13 μm SiGe BiCMOS consumes 8W of power [2]...

A compact parallel optical receiver consisting of a four-channel 25-Gb/s CMOS transimpedance-amplifier (TIA) array and a PIN-PD array for board-to-board optical interconnects was developed. Both arrays are directly mounted on a multi-layer ceramic package. The 25-Gb/s TIA array was fabricated by using 65-nm CMOS technology. To improve gain flatness...

An integrated 100-Gb/s receiver, which consists of a four-channel 25 Gb/s CMOS trans-impedance amplifier and PIN-PD arrays, was fabricated for high sensitivity (-8.1 dBm), small inter-channel crosstalk (0.8 dB), and low-power (3.0 mW/Gb/s) operation.

A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equ...

This article discusses the logical implementation of the media access control and the physical layer of 100 Gb/s Ethernet. The target are a MAC/PCS LSI, supporting MAC and physical coding sublayer, and a gearbox LSI, providing 10:4 parallel lane-width exchange inside an optical module. The two LSIs are connected by a 100 gigabit attachment unit int...

The next-generation cloud computing systems are expected to be connected to the real world more tightly by massive amounts of sensors and actuators. Today's clouds, however, are not capable of handling massive sensor data or giving fast feedback to the real world because of the long latency and limited bandwidth of WANs. We propose a cloud architec...

ICT (Information and communication technology) has continued its progress to improve our lives. While environmental protection and effective use of energy has become a concern of the whole human society, ICT is now required to become not only business tool but also an essential technology for the society by means of environmental protection and ene...

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We worked on the physical layer model for implementing the optical DQPSK transmission function. In order to enable a high speed DQPSK transmission, a signal multiplexing and de-multiplexing module was needed. The multiplexing and de-multiplexing module exchanges a high frequency 2bit width data signal and a low frequency wide width data signal into...

In this paper, future requirements we believe that will be needed for achieving power efficient routers are shown. The optical backplane is a proposal technology we are working on, which enables a high-speed and power efficient data transmission in backplane of routers and switches, by connecting the electronic devices together with optical paths....

A high-throughput and high-reliable physical-layer architecture for very-short-reach (VSR) and backplane Ethernet applications was developed. VSR and backplane networks provide 100-Gb/s data transmission between blade servers and LAN switches. This architecture supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, makin...

Cognitive radio system consists of multiple wireless accesses that cover overlapping area, and cognitive terminals that use one or more of the wireless accesses simultaneously. In this paper, we present the architecture of the cognitive radio system that we proposed. In the proposed architecture, each cognitive terminal, that has multiple radio sys...

A high-speed physical-layer architecture for next-generation higher-speed Ethernet for VSR and backplane applications was developed. VSR and backplane networks provide 100-Gb/s data transmission in “mega data centers” and blade servers, which have new and broad potential markets of LAN technologies. It supports 100-Gb/s-throughput, high-reliability...

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation...

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 × 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiple...

Conventionally, inner layer wires using via holes that have large losses are not intended for high-speed electrical signal transmission in 10 Gbit/s printed-circuit boards (using the 7-GHz evaluation standard bandwidth), so only dedicated surface wires are used. However, surface wiring has a two-dimensional wiring layout and is not suited to high-d...

An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks. A parallel link of 12 10-Gb/s synchronized parallel optical lanes is proposed. The 10 optical lanes are used to transmit 10-bit parallel data. The one of redundant lanes transmits a forward er...

The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain t...

RHiNET-3/SW is the third-generation switch used in the RHiNET-3 system. It provides both low-latency processing and flexible connection due to its use of a credit-based flow-control mechanism, topology-free routing, and deadlock-free routing. The aggregate throughput of RHiNET-3/SW is 80 Gbps, and the latency is 140 ns. RHiNET-3/SW also provides a...

We developed the RHiNET-2/SW high-speed network switch for a high-throughput parallel computing system consisting of optically interconnected distributed personal computers (PCs). RHiNET-2/SW enables high-throughput network switching (64 Gbit/s) by means of a switching LSI and eight pairs of synchronized parallel optical interconnection modules. To...

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RHiNET-2/SW is a network switch for the RHiNET-2 parallel computing system. RHiNET-2/SW enables high-speed and long-distance data transmission between PC nodes for parallel computing. In RHiNET-2/SW, a one-chip CMOS switch-LSI and eight pairs of 800-Mbit/s x 12-channel parallel optical interconnection modules are mounted into a single compact board...

We have developed a prototype network switch, RHiNET-3/SW, for a RHiNET high-performance distributed parallel computing environment. It has eight I/O ports and each port provides high-speed, bi-directional 10-Gbit/s-per-port parallel optical data transmission in a distance of over 300 m. The aggregate throughput is 80 Gbit/s per board. A switch con...

RHiNET-2/SW is a network switch that enables high-performance optical network based parallel computing system in a distributed environment. The switch used in such a computing system must provide high-speed, low-latency packet switching with high reliability. Our switch allows high-speed 8-Gb/s/port optical data transmission over a distance of up t...

A local area distributed computing system called RHiNET (RWCP High Performance Network), in which thousands of commodity personal computers and workstations can be connected by high speed optical interconnection is being developed. RHiNET consists of network interfaces, network switches and optical interconnections. RHiNET will provide a single sys...

We have produced a prototype network-switch board (the RHiNET-2/SW) for optical interconnection. Eight pairs of 800-Mbit/s X 12-channel optical interconnection modules and a one-chip CMOS ASIC switch LSI (a 784-pin BGA package) are mounted on to a single board. This board allows 8- Gbit/s/port parallel optical data transmission over a distance of u...

Optical interconnection has been implemented to interconnect the nodes of the RWC-1 massively parallel computer. This interconnect enables large-throughput, long-transmission-length, low-latency, and highly transparent fundamental internode communication. An eight-node parallel processing system was thus produced as a prototype. Each node is interc...

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency ``zero-copy''communication in multi-tasking environments. Eight pairs of 800-Mbit/s 12-channel optical interconnection modules and a CMOS ASIC switch are implemented o...

Optical interconnection between the nodes of the RWC-1 massively parallel computer has been implemented. A one-node testbed system and an eight-node parallel processing system have been produced to demonstrate large-throughput small-skew low-latency and highly reliable optical internode connection. Each node was interconnected through dc-coupled 24...

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency “zero-copy” communication in multi-tasking environments. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are implemented on...

We produced a large-throughput optical interconnection for a distributed parallel computing system. It transmits optical data at a rate of over 800-Mbit/s×10-bit through a 50-m single-mode fiber, using a CMOS MUX/DEMUX and retiming circuits. We measured the BER to be less than 10^-9

We have built an optical interconnection subsystem to interconnect the nodes of a massively parallel computer, and have achieved highly reliable 48-bit synchronized parallel- optical-data transmission (600-MB/s throughput).

An optical inter-node connection in a massively parallel computer testbed was used in order to determine whether large throughput highly reliable inter-node communication is attainable. Highly reliable 48-b parallel-data transmission at 100 MHz (600-MB/s throughput) was achieved. For error-free data transmission, the total skew in the inter-node da...

The introduction of optical interconnections to internode connections in the RWC-1 massively parallel computer testbed, which was designed to demonstrate fundamental internode communications, and uses eight pairs of 12-channel compact optical modules, has enabled 48-b parallel data transmission at 100 MHz (600-MB/s throughput), to be achieved in fi...

Synchronously Parallel fiber optical interconnection technologies are attractive for high- throughput computer and switching systems, such as massively parallel computers and ATM switches. Because they would be able to eliminate a connection bottleneck caused by conventional copper cables using optical fibers featured in high-speed and long-distanc...

A large number of activities on 2 dimensional optical devices for free space optical interconnection have been done in order to attain a large interconnection through-put for optical computing. In addition to the space domain processing, optical frequency domain data processing can realize the larger through-put by means of a multi-dimensional inte...

A lossless and low crosstalk optical switch is most desirable for large scale photonic networks. To realize such a switch, a traveling-wave amplifier is integrated into the slip waveguide of a carrier-injection type optical single-slip structure(S ³ ) switch. Fiber-to-fiber lossless and low crosstalk (an ON/OFF ratio as high as 40dB) are demonstrat...

Photonic space division switching networks are one of the most promising switching systems. In designing such a network on a large scale, C. Burke et al. proposed and demonstrated that use of semiconductor optical amplifiers could reduce optical switch loss[1]. A lossless optical switch unit is most desirable for large scale photonic networks becau...

The field-induced refractive index change of an InGaAs/InAlAs MQW waveguide is examined for various wavelengths and TE/TM modes using a MZ modulator. The quadratic EO coefficients in the MQW waveguide for both TE and TM modes due to quantum confined Stark effect (QCSE) is on the order of 10/sup -18/ (m/sup 2//V/sup 2/), which is dominant compared w...

: Field-induced refractive index change(Electro-refraction;ER) in multi-quantum well (MQW) structures arising from QCSE have become increasingly attractive for applications, especially in high speed, long-haul optical transmission systems. Because they have potential for low chirp, high speed modulation and for opto-electronic integration. Recently...

In a parabolic quantum well, the shift in optical transition energy due to the quantum confined Stark effect is independent of the carrier effective mass. This fact enables us to realize polarization‐independent optical waveguide intensity switches with high on/off ratio. An absorption‐type switch with GaAs/Al 0.3 Ga 0.7 As equivalent parabolic qua...

Carrier confinement in semiconductor quantum wells(QWs) results in extremely large exciton binding energy and oscillator strength when compared with those of bulk crystals. Under an electric field applied perpendicular to the QW layer, the energy of the fundamental absorption edge shifts by a large amount without severe line broadening of the excit...

Quantum-confined Stark effect in parabolic quantum well (PQW) has been analyzed both analytically and numerically. Analytical studies have revealed that the fundamental absorption edge shift in PQWs is proportional to the square of the well width, and that the Stark shift in PQWs is independent of the particle mass. From numerical calculations, it...

Cognitive radio system consists of multiple wireless accesses that cover overlapping area, and cognitive terminals that use one or more of the wireless accesses simultaneously. In this paper, we propose the architecture of the cognitive radio system, and the inter-system handover protocols. In the proposed architecture, each cognitive terminal, tha...