Shilpi Birla

Manipal University Jaipur · Department of Electronics and Communication Engineering

Downscaling of metal oxide semiconductor field effect transistors (MOSFET) has resulted in increased short channel effects (SCEs), off-leakage current and subthreshold swing. At room temperature, the minimum subthreshold swing for MOSFETs is 60 mV/dec. So, MOSFET is not suitable for the deep submicron regime. A new device structure is being investi...

The scalability of bulk CMOS faced various possible issues due to inherent material and process innovation constraints. Alternatively, transistor devices with supplementary gates, such as the Fin Field-effect transistor (FinFET) structure has attracted developing interest during the last few generations of their emergence, attributable to the appro...

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD=0.3V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST...

The revolution in technology is so fast that even silicon devices are not able to meet the current demand of high speed, low power, and minimal area. The CMOS SRAM cells are the ones, affected the most by the revolutionary scaling of the devices. Due to various limitations of CMOS in deep sub-micron, new devices have emerged. One such device is the...

The modern system-on-chips require stable and low-power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability- and power-improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross-coupled structure of a conventional inverter with a N-type stacked transistor and a Schmi...

Most of the high-speed circuits use static random access memory (SRAM) to store electronics data on-chip. The necessity of designing low-area and high-speed integrated circuits (ICs) leads to scaling the CMOS devices. The limitation of MOSFET scaling introduced the new transistor technology. The paper introduced the comparative analysis of 10T SRAM...

Technology node modification is the demand of the present era of the IC industry. Conventional CMOS to FINFET and now CNTFET is playing a major role to fulfill this demand because beyond the 7 nm technology node CNTFET shows the same performance and is not affected by the issues coming from the short channel effect. Meanwhile, memory cells are also...

Since the CMOS technology has reached to nanometer regime to meet the increasing demand of smarter and faster device, CMOS circuits have to face various short channel effects and variation in process parameters leading to degradation in performance and reliability. CMOS SRAM is one of the major circuits which degrades its performance due to short c...

This work presents gate-oxide variation effect on the performance of cylindrical surrounding double-gate (CSDG) MOSFET, particularly the device saturation operation. The analysis is based upon the resemblance of the device oxide capacitance in the device pinch-off. The capacitance formation at pinch-off cannot be considered a cylindrical parallel p...

With the advent of microelectronics, the scaling of a transistor had become challenging due to the several factors out of which dynamic power is one of the important factors to be dealt with. With the reduction in chip area need of low power circuits increased, these circuits would consume less dynamic power. Static CMOS logic implementation is a w...

This paper explores an ultra-low-power 10T subthreshold SRAM with high stabilities based on 10-nm FinFETs. To prove the superiority of the proposed 10T SRAM's performance, a comparison has been done with existing SRAMs such as the 6T, ST2, DIRP10T, PPN10T, and FC11T at VDD = 0.3 V. The proposed cell offers 2.08X/1.31X/1.03X higher read-stability co...

CNTFET is more prominent for its performance when compared with conventional CMOS even beyond the 10 nm technology node because of its excellent thermal conductivities, superior current capabilities, and ballistic transport operation. CNTFET based SRAM cell is already available with 6 T, 7 T, 8 T, 9 T, and 10 T, etc. on behalf of detailed literatur...

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. Th...

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely...

Nanotechnology refers to specifically designed materials as well as devices that possess a minimum of one of their dimensions confined within the range of 1 nm to 100 nm. On specific reference to the electronic properties of materials under the necessary confinement of one of the dimensions, the sub-branch is called nanoelectronics. Nanoelectronics...

In ultra-scaled device design, it is vital to incorporate the quantum-mechanical effects since charge confinement governs the inversion in the semiconductor at smaller dimensions. In this paper, the authors have first-ever analyzed the quantum confinement effect for Cylindrical Surrounding Double-Gate (CSDG) MOSFET structure and developed a physica...

High-quality n-ZnO/AlN/p-Si and n-ZnO/p-Si heterojunction diodes were successfully fabricated by RF sputtering deposition technique. XRD, SEM, and EDX measurements confirm the excellent structural and surface morphological attributes of the grown ZnO thin films. I−V measurements were performed and a good rectification ratio of ~ 319 was found for b...

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more co...

Due to the scaling, many limitation arised for CMOS-based design memory cells in the nanometer regime i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of electronics industry in many applications such as Internet of things (IoT), Electronics gadgets e.g. Mobile, Laptop...

Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to the high demand for large density. Fin-shaped field-effect transistor (FinFE...

iopscience.iop.org A 4× 4 8T-SRAM array with single-ended read and differential write scheme for low voltage applications Chusen Duari, Shilpi Birla, Amit Kumar Singh Semiconductor Science and Technology 36 (6), 065013, 2021 In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it pl...

This article aims to provide a wide comparative analysis of different SRAM cells in 7nm FinFET Technology. Due to various limitations of the CMOS device in nanotechnology, FinFET is one of the trending choices for memory designers which can improve the stability and minimize the Short Channel Effects of the CMOS. Here, performance metrics of these...

The temperature dependent electrical transport properties of n-ZnO/AlN/p-Si heterojunction diode fabricated by RF sputtering system have been investigated over a wide temperature range of 303 K–413 K. The AlN buffer layer in-between ZnO and Si lowers the mismatch in thermal expansion coefficient/lattice constant for improved electrical and structur...

In ultra-low-power applications, the design of power-efficient static random access memory (SRAM) is a major concern as it plays a significant part in leakage due to its higher density. In this paper, we have designed a power-efficient SRAM array that efficiently utilizes our SRAM cell for low-power and reliable memory applications. The proposed SR...

Excellent thermal conductivities, superior current capabilities and ballistic transport operation these prominent properties of carbon nanotube field-effect transistor technology make it superior or alternative approach over traditional CMOS and conventional FETs. A detailed simulation-based analysis of this technology with the evaluation of circui...

Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor...

Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consu...

With the world maturing, constant infections are turning into significant reasons for death around the globe. The chronic diseases are taking millions of lives every year. The perception about chronic disease is that if people can be diagnosed early, it is better for the patient to get treatments. A couple examples are blood glucose level and arrhy...

The invention is to provide an ATM which is easy to use even for the people who lives in rural area. The ATM will be installed at the nearest POST Office. This ATM will consider their Aadhar Number as their account number. The Village ATM is biometric in nature. The machine accepts the fingerprints and the user can do the transactions. It is differ...

Since miniaturization of CMOS has taken place speed and power are the most important parameters for any circuit, like speed of an adder is a critical parameter in the overall performance of an Arithmetic Logic Unit (ALU). In order to identify the best suitable 2-bit adder in terms of speed, power dissipation, area and leakage current a comparative...

Digital Image Watermarking using Singular Value Decomposition has a fundamental flaw of false watermark generation when Singular Values of the watermark are embedded into the cover. The proposed work embeds Principal Components of two watermarks instead, to overcome this flaw. These watermarks are embedded into horizontal and vertical sub-band coef...

For IoT applications, a new SRAM cell with differential write and single-ended read ability is proposed in this paper. The transmission gate is used as an access transistor to get rail to the rail voltage swing and improved stability. Analysis of leakage power and stability for proposed SRAM cell at supply voltage ranging from 0.9V to 0.5V is compa...

In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages t...

The limitations of the CMOS scaling has opened the path for Nano-Scaled devices. FinFET is one of the promising devices after CMOS with a great feature of low leakage. Since the inception of hand help devices, SRAM memories play a vital role in the performance of these devices. Thus, a need for stable, low power SRAM memories is in demand. In this...

Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive f...

In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which...

In traditional verification environment, hardware and software involve isolated design and verification. Due to the demise of Moore's law, the processor's frequency is no longer increasing. This demise of Moore's law and time-to-market pressures drive the wave of new technology where hardware and software are tightly integrated. This is done in ord...

With the ease of availability and accessibility of the internet and image processing software, it has become difficult to distinguish between the original and manipulated images. To restore this lost trust in digital images, digital image watermarking is widely used. Some owner’s information is embedded within the digital image which is not only re...

Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circ...

The explosive growth of battery operated semiconductor devices has made low-power design a priority in recent years. The effect of temperature on the leakage currents is coming as a future challenge in the high density CMOS based portable mobile multimedia rich applications. In this paper the standby leakage power analysis at different operating te...

In modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time. The d...

In this paper, we present the analysis of subthreshold leakage current with temperature variations in an IP3 SRAM bit-cell. A comparison of subthreshold leakage current of IP3 SRAM bit-cell with conventional 6T, P4 and P3 is performed at elevated temperatures ranging from 0 0 C to 125 0 C. It is observed that subthreshold leakage increases with tem...

Due to the continuous rising demand of handheld devices like iPods, mobile, tablets; specific applications like bio-medical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) s...

In this work, the analysis and simulation work is proposed for the low-power (reduced subthreshold leakage) and high performance SRAM bit-cells for mobile multimedia applications in deep-sub-micron (DSM) CMOS technology. The sub-threshold leakage analysis of the P3 SRAM cell has been carried out. It has been observed that due to pMOS stacking and f...

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the V dd reduces the...

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been in...

In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an in...

For mobile and multimedia applications of SRAMs, there is a strong need to reduce standby current leakages while keeping the memory cell data unchanged. To meet this objective, various techniques have been developed to reduce the leakage current at the process/device, circuit, architecture, and algorithmic levels. The traditional 6T CMOS SRAMs face...

The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation...

In the era of the digital VLSI design, there are times when a designer needs to interface two systems working at two different clocks frequencies. This interfacing is difficult in the sense that design becomes asynchronous at the boundary of interface, which directly results in setup-time and hold-time violations, metastability and unreliable data...

Due to CMOS technology scaling and the need of battery operated devices continues to drive the increase of on-die memory density to meet performance needs in various applications. Meanwhile, the device variation and leakage are increasing as the miniaturization of the transistor continues which also effects the realiability and erformance of the de...

The emerging Wireless Sensor Network technologies are facilitating novel applications in health monitoring, industrial monitoring and security surveillance. The small physical dimensions of wireless sensor nodes often restrict the energy source to a small battery. The limited energy consumption requirement demands for ultra-low power sensing, proce...

The growing demand in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumptio...

The High leakage current in deep sub-micrometer region is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltage, channel length, and the gate oxide thickness are reduced. As the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data ret...

Spiral Inductors suffer from complex loss mechanism in the metal and substrate and consume large chip area making them difficult to characterize and expensive to implement. The performance of on chip spiral inductors is a limiting factor. The spiral inductor design space is complex and innovative optimization and synthesis techniques are required t...

The term "packaging" has its role as: 1) Provide I/O connections to the semiconductor devices so the IC is tested and ready for board assembly. This is called IC packaging. 2) Integrate components into systems to form end product systems such as cell phones, PDAs, Laptops. This is called system packaging. Both the above IC and systems packaging are...

The ICACTE 2009 was organized to gather members of the international community of Computer Theory and Engineering scientists so that researchers from around the world could present their leading-edge work, expanding our community's knowledge and insight into the significant challenges currently being addressed in that research.

The ICACTE 2009 was organized to gather members of the international community of Computer Theory and Engineering scientists so that researchers from around the world could present their leading-edge work, expanding our community's knowledge and insight into the significant challenges currently being addressed in that research.

Ultra low-power applications have gained a lot of attention in recent years. This is due to the increase in battery operated devices and also due to the scaling of CMOS devices. Various CMOS circuits of low-leakage are in demand one of them is the SRAM. So, at the present scenario various technologies are used to design the low leakage SRAM. The lo...

A considerate debate between open source and proprietary softwares is going on from years now. But, with the success of Linux, Apache, Android, etc. a whole new dimension has been added to this debate. As the open source is growing day by day in the corporate world but there are less number of people contributing to open source community and the re...

In the present scenario battery-powered hand-held multimedia systems are becoming more and more popular day by day. But as the CMOS technology has been continuously scaled down so it has been a major thrust to improve the performance and robustness of the memory used in these devices. The process variations which mainly include the random threshold...