Serdar Özoguz

Istanbul Technical University · Department of Electronics and Communication Engineering

This study presents an automated high-accuracy optimization approach for designing high-performance radio frequency high power amplifiers (HPAs). The amplifier is designed by applying a top-down pruning optimization approach that automatically converts the given HPA with lumped elements (LEs) to the HPA with distributed elements (DEs). Firstly, the...

Optimizations have gained much consideration from the researchers working in the domains of analog and radio frequency (RF), recently. Dealing with highly nonlinear behavior of active components and aiming to meet design specifications are common issues in all nonlinear circuit designs. As a consequence and accordingly, many studies have been condu...

Optimizations have gained much consideration from the researchers working in the domains of analog and radio frequency (RF), recently. Dealing with highly nonlinear behavior of active components and aiming to meet design specifications are common issues in all nonlinear circuit designs. As a consequence and accordingly, many studies have been condu...

In this paper, we propose a modular Constant Phase Element (CPE) emulator, the approximation order of which is electronically adjustable. In this way, the emulator provides a limited approximation error over a range of the parameter alpha, the order of the CPE. A fractional-order differentiator has been utilized in the emulator, which is realized b...

This study presents an automated optimization-oriented strategy for designing high power amplifiers (HPAs) using deep neural networks (DNNs). The proposed strategy consists of two optimization phases that are applied sequentially. In the first phase, the circuit topology is optimized by determining the number of passive components in the input and...

Power amplifier (PA) designs at high frequency are not straightforward and they depend on designers’ experience by dealing with a high number of parameters to be set. To address PA design problems, we propose an automated bottomup method based on an artificial neural network (ANN) to be employed in the optimization-oriented strategy. The proposed m...

This study presents an automated RF power amplifier design procedure and methods which aim to convert systematically built-in lumped elements to distributed elements by simultaneously optimizing power gain, output power and efficiency. This approach which is performed by using Bayesian optimization results in ready-to-fabricate optimized designs wi...

This study describes a design automation methodology and technique for designing an optimized high power amplifier (PA). The proposed method optimizes the matching networks by deriving the suitable matching components and automatically evaluating their performances with nonlinear simulations. The design process starts with a simple cell and then th...

In radio frequency power amplifier designs, the desired current and voltage waveforms are achieved through the tuning of the fundamental and harmonic impedance values in the matching networks. Analytical design methods have been often used to design power amplifiers. But nonlinear behavior of the high-frequency power transistors and inevitable trad...

In this paper, CMOS realizations of exponential function generators are considered and it is shown that the inherent square-law characteristic of the CMOS can be effectively used to produce the required exponential characteristic. While many of the existing exponential function generators rely on complicated coefficient settings procedure, in order...

In this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured with perpendicular magnetic tunnel junctions with a high tunneling magnetoresistance ratio in a low resistance-area product. To overcome the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its per...

High data rate mobile communication requires wideband high-frequency circuits and systems. A high power amplifier (HPA) is an essential part of the communication systems and operates at saturation to achieve high efficiency. On the other hand, the design of an HPA is a challenging issue due to the nonlinear behavior of the high frequency and high p...

In this paper, a set of current-mode MOSFET-C multifunction filters are presented. Since MOS transistors operating in saturation region are used instead of the passive resistors, key filter parameters are all electronically controllable. The main properties of a total of eight different multifunction filters are catalogued in tabular form. The prop...

STT-MRAM with interfacial-anisotropy-type perpendicular MTJ (IPMTJ) is a powerful candidate for the low switching energy design of STT-MRAM. In the literature, the reading operation of STT-MRAM structured with IPMTJs have been not studied until this time, in our knowledge. We investigated the reading operation of STT-MRAM structured with IPMTJs. To...

This paper presents a comprehensive method and analysis on the design of two-transistor multi-output filters Q1 where three possible functions are simultaneously available. Although two transistors are employed at its core, proper biasing does not require additional passive components. A total of thirteen valid second-order filters are reported, an...

In this paper, the use of MOS-only active filters in the implementation of area-effective low-IF image reject filters is discussed. For this purpose, complex filter design procedure is considered regarding MOS-only filter realization techniques and a new second-order filter topology which favors filter’s area-effective implementation is proposed. O...

In this paper, the common-base (or-gate) differential amplifier is revisited and presented. A variant of the same amplifier is also presented and both are analyzed using standard two-port network analysis. Their high frequency behavior, differences in biasing details and noise analysis are also compared and contrasted. New differential input-output filte...

In order to provide a systematic approach to the realization of filters with small chip area, two techniques which lead to a substantial reduction in the chip area occupied by MOSFET-C filters are proposed. The first method is based on using capacitance multipliers, while the second method relies on modifying the given circuit by appropriately addi...

A new dynamical neuron model for low power and compact VLSI implementation is presented. The model is capable of generating the most common type of spiking patterns. Judicious use of subthreshold CMOS design techniques leads to a very effective low-power CMOS Neuron and synapse circuits. The circuit consists of a single first-order log domain filte...

In this paper, a simple filter topology that can be used to implement first-order MOS-only allpass filter is proposed. The proposed MOS-only allpass filter offers inherently very accurate magnitude and phase characteristics at very high frequencies. However, MOS-only active filter suffers from an inherent low frequency limitation. In order to addre...

This paper presents a new dynamical neuron model which is appropriate for electronic circuit implementation and its low power, compact VLSI implementation. The neuron circuit consists of one first-order log domain filters, hyperbolic type nonlinear function generator and resetting circuitry. Owing to the log domain design and current-mode operation...

Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, lo...

This paper presents a new current-mode CMOS loser-take-all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi-input configuration by repeating the cell for each additional input. A high-speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of...

In this paper, circuit implementation of diamond-shaped type-2 membership function in CMOS technology is presented. Designing of mixed analog/digital circuits provides a flexible configuration as well as the highly accurate performance, where analog circuits are employed to realize required functions, while the programmable units implemented using...

In this paper, a MOS-only multifunction filter which simultaneously realizes second-order lowpass and bandpass functions is presented. It is shown that the filter offers very useful advantages, such as low occupied chip area and suitability for high-frequency operation. Although the operation frequency range of the filter is found to be limited, a...

Although the design of integrated filters using MOS-only circuits provides some vital advantages, these circuits are inherently prone to have limited operating frequency range. This fact leads to a poor tunability range and seriously degrades the usefulness of this class of filters. In order to address this issue, two methods are presented and deta...

Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of bi...

The main implementation issues of chaotic circuits based on time-delay models are discussed and a sampled-data chaotic system is presented to address this issue. Detailed numerical simulations revealing system chaotic behavior are provided. In order to illustrate the usefulness of the chaotic circuit, the design of a high-performance true random bi...

The objective of this paper is to present a modification technique that can be used to alleviate the low-frequency limitations of MOS-only filters. The technique is based on adding an additional pair of cross-coupled transistors to modify the time constant of the filter. In this case, lower frequency operations is attainable without having to use l...

In this paper, a new CMOS four-quadrant analog multiplier circuit is proposed, based on a pair of dual- Translinear loops. The significant features of the circuit are its high accuracy and high linearity as well as its body effect-free operation, owing to the fact that the circuit relies on a new dual-translinear topology. In addition, harmonic dis...

Volterra analysis can be used to perform distortion contribution analysis. It is shown here that an ordinary time-invariant (TI) Volterra analysis with fitted polynomial models can be used in such a non-linear application as mixers and switching power ...

The objective of this paper is to present a simple filter topology, which can be used to implement first- and second-order MOS-only allpass filters. The resulting filters realize the allpass functions without using any external passive components; hence these occupy very small chip area and are capable of operating at high frequencies. Cadence Spec...

A new class of active filters, real active-only filters, is described and possible implementation issues of these filters are discussed. To remedy these issues, a fullydifferential active-only integrator block built around current controlled current conveyors is presented. The integration frequency of the proposed circuit is adjustable over a wide...

In order to overcome some practical design and implementation issues of real active-only filters, a lossless integrator that employs one current controlled current conveyor and one voltage buffer with adjustable gain is presented. A real active-only filter circuit based on this integrator block is presented and designed. The feasibility of this fil...

Two novel circuit-independent RC nonautonomous chaotic oscillator structures are presented. Both structures rely on a periodic pulse-train as the driving force and on a comparator as the only source of nonlinearity.

In this paper, a new CMOS exponential circuit with improved linear output range is presented. The proposed circuit is based on a new approximation function to increase the dB- linear output range. Simulation results in a 0.35 µm standard CMOS technology using HSPICE reveal an output range of 78 dB with errors less than ±1 dB. Also the Monte-Carlo s...

We present a low-power VLSI implementation of the Izhikevich neuron model utilizing two first-order log-domain filters as the main building block. One of the filters includes an active diode connection in order to lower current levels to obtain a low-power, large time constant design. Thus, the neuron circuit operates in sub-threshold regime with b...

CMOS realization of a one-dimensional cellular neural network containing twenty cells is presented. The network consists of relaxation oscillators and it has been designed to generate autowaves. The layout design of the circuit has been done in the Cadence environment. The test results of the fabricated chip are included.

An A/D converter based random bit generator which exploits continuous-time chaos is presented. The chaotic circuit, which is used as the core of the random bit generator generates double-scroll attractor the frequency spectrum of which spans up to 80 MHz. The chaotic circuit was fabricated using a 0.35 μm CMOS process and the chip area, excludin...

In this paper, the generation of multiscroll chaotic attractors derived from a time-delay differential equation is presented. The proposed system is represented by only one first-order differential equation including time-delayed state variable, and employs hysteresis function as the nonlinear characteristic. The generalization of the introduced sy...

Two novel sinusoidal oscillator structures with an explicit tanh(x) nonlinearity are proposed. The oscillators have the attractive feature: the higher the operating frequency, the lower the necessary gain required to start oscillations. A nonlinear model for the two oscillators is derived and verified numerically. Spice simulations using AMS BiCMOS...

In this work, an integrated random number generator based on oscillator sampling method is presented. The random number generator exploits a continuous-time chaotic circuit as the entropy source. A source-coupled multivibrator is used to transform the generated chaotic signal into jittered oscillations required in the oscillator sampling method. Th...

We propose a novel RC sinusoidal oscillator architecture suitable for very low frequency generation. The oscillator is also attractive in the sense that the lower the oscillation frequency, the lower the necessary gain required to start oscillations. Further, the proposed architecture is active-circuit-independent and can be realized in any suitabl...

In this paper a CMOS realization of a linearly weighted classifier circuit which is called classifier block is proposed. The proposed classifier block is composed of linearly weighted circuits (LWC) and CMOS core circuits (CC). The proposed circuit can classify linearly non-separable data. The weights of the classifier circuit are achieved with LWC...

In this paper, we provide the first experimental proof for the existence of rank 1 chaos in the switch-controlled Chua circuit by following a step-by-step procedure given by the theory of rank 1 maps. At the center of this procedure is a periodically kicked limit cycle obtained from the unforced system. Then, this limit cycle is subjected to period...

A new cross-coupled LC chaos oscillator suitable for IC realisation is presented. The proposed circuit was fabricated using a 0.35 mum CMOS process and test results showing its feasibility are given. As a possible application, a method for using the proposed oscillator as the core of a random number generator is described. Experimental binary data...

Two chaotic oscillators, which generate butterfly chaotic attractors, are presented. Both systems are based on the same second-order multiplier-free subsystem; hence they have simple circuit implementations. Derivation of more complicated attractors, i.e. multi-wing butterfly attractors is also described. Experimental results from the constructed c...

Bu çalışmada tamamen tümleştirmeye uygun gerçek rastgele sayı üreteci (GRSÜ) devresi tasarlanmıştır. Tasarımda osilatör örnekleme yöntemi kullanılmıştır. RSÜ yapısında gerçek rastgeleliği sağlamak amacıyla belirsizlik kaynağı olarak sürekli zamanlı kaotik devre kullanılmıştır. Kaotik devre negatif-gm LC osilatör tabanlıdır. Kaotik işaret multivibra...

In this paper, a CMOS design of a network of relaxation oscillators is described. The parasitic gate-source capacitances of the MOS transistors are used to implement fast state variable of the relaxation oscillator. It is shown that circuit realization of the relaxation oscillators produces various dynamic behaviour. Simulations of the designed net...

In this paper, synchronization of two n-scroll chaotic attractor systems, which are obtained from first-order time-delay differential equations, is presented. Synchronization between different state variables is observed with different types of coupling configuration. Among them there is also one special kind of synchronization, which is called "an...

A new chaotic oscillator which can be implemented on standard CMOS process is presented. The circuit generates double-scroll chaotic attractor and is suitable for high-frequency operation. As a possible application, the use of the circuit as the core of a random number generator (RNG) is illustrated. The quality of the RNG is investigated using sta...

In this work, a new random number generator circuit using continuous-time chaos is described. The circuit is based on the classical dual oscillator sampling technique. In the classical approaches, the jittered oscillations used in this technique are obtained using a physical noise. In this work, we propose to use continuous-time chaos to generate t...

A system for generating a multi-butterfly chaotic attractor using the multi-level-logic pulse-excitation technique is proposed. Two-butterfly, three-butterfly and four-butterfly attractors are demonstrated. Results from an experimental setup are also shown.

In this paper, a novel first-order delay differential equation capable of generating n-scroll chaotic attractor is presented. Hopf bifurcation of the introduced n-scroll chaotic system is analytically and numerically determined. The bifurcation diagram and Lyapunov spectrum of the system are calculated and the results show that the system has a cha...

Two integrated chaotic oscillators based on negative- gm LC tank circuit are presented. Simulations using Spectre in CADENCE design tools show that one of the proposed circuits generates chaos in the gigahertz frequency region. The applications of the chaotic circuits in random bit generations are also described. Experimental results using standard...

A novel random number generator (RNG) based on an autonomous continuous-time chaotic oscillator is presented. In the proposed RNG, dual oscillator architecture is used with the chaotic oscillator in order to increase the throughput and to maximize the statistical quality of the output sequence. Mathematical model of the proposed design has been dev...

Class-AB squaring circuits based on classical mixed four-transistor translinear cell are found to have large sensitivity with respect to the mismatches of the transistors involved in the translinear loop. In order to reduce this sensitivity, we propose the use of differentially driven mixed translinear cells. Using this cell, a voltage squaring cir...

We show how the hysteresis behavior in electronic circuits can be explained in a robust manner using PSpice transient simulations. Furthermore, we design a novel circuit for three-segment nonlinear characteristic shaping and show how this circuit can be used to produce hysteresis loops. The realization of relaxation oscillators is then given as a t...

Two integrated continuous-time chaotic oscillators based on cross-coupled -g_m oscillators are presented and their application to random bit generation is described. Numerical and experimental results show that the generated binary streams pass standard randomness statistical tests. Simulation using Cadence verifies possible circuit opera...

Two new random number generators (RNGs) based on a double-scroll attractor are presented. Simulation and experimental results, verifying the feasibility of the circuits, are given. We have numerically verified that the bit streams, obtained from the 1D Poincare section of the system, when the map was divided into regions according to distribution,...

We investigate the possibility of generating higher order chaos via passive coupling of two identical or nonidentical sinusoidal oscillators. The examples of such a technique, which have already been reported in the literature, suffer from the lack of generality and apply only to particular sinusoidal oscillator circuits. Here, we treat sinusoidal...

We investigate the possibility of generating higher order chaos via passive coupling of two identical or nonidentical sinusoidal oscillators. The examples of such a technique, which have already been reported in the literature, suffer from the lack of generality and apply only to particular sinusoidal oscillator circuits. Here, we treat sinusoidal...

Chaotic oscillators capable of generating 2D scroll grid attractors are designed based on a recently proposed nonautonomous design technique. The technique relies on modifying the system equilibrium points via multiple external periodical pulse excitations. Numerical and experimental results verifying the theory are included

A novel approximate square-root domain all-pass filter operating from a single 3.3 V supply is reported. The circuit requires a small number of transistors, with a bandwidth exceeding 100 MHz. Two-phase and three-phase oscillators based on cascaded sections of the proposed filter are constructed followed by a generic multiphase oscillator. Simulati...

Chaotic oscillators capable of generating 2-D scroll grid attractors are designed based on a recently proposed nonautonomous design technique. The technique relies on modifying the system equilibrium points via multiple external periodical pulse excitations. Numerical and experimental results verifying the theory are included.

A non-autonomous chaotic circuit which is suitable for high-frequency IC realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincaré map of the system passed the four basic tests of FIPS-140-1 test suite. W...

Two novel circuit-independent RC nonautonomous chaotic oscillator structures are presented. Both structures rely on a periodic pulse-train as the driving force and on a comparator as the only source of nonlinearity. These oscillators are suitable for generation of pseudo-random sequences in digitally clocked systems and can perform as periodic-to-c...

An integrated continuous-time chaotic oscillator capable of operating at very high frequencies is presented and its application to a high-speed random bit generator is described. Numerical and experimental results show that the generated binary streams pass standard statistical tests. Simulation using CADENCE tools also verifies that the circuit op...

A non-autonomous chaotic circuit which is suitable for high-frequency IC realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincare map of the system passed the four basic tests of FIPS-140-1 test suite. W...

A nonautonomous chaotic circuit which is suitable for high-frequency IC realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincare map of the system passed the four basic tests of FIPS-140-1 test suite. Fi...

A novel high-performance first-order all-pass filter employing a single active element and a minimum number of passive components is presented. The proposed circuit is based on differential difference amplifier and is very suitable for low voltage operation. Also, the use of grounded capacitor enables its implementation with standard CMOS technolog...

The aim of this paper is to present a simple circuit design method for realizing a nonautonomous chaotic oscillator given a second-order sinusoidal oscillator with two capacitors. The proposed method relies on applying a periodic pulse train, as an exciting source, and the addition of a signum-type nonlinear transconductor to the given sinusoidal o...

We first present a simple circuit design method for obtaining a non-autonomous chaotic oscillator circuit from any given second-order sinusoidal oscillator with two capacitors. The proposed method relies on applying a periodic pulse train as the excitation source and an addition of signum-type nonlinear self-feedback to the given sinusoidal oscilla...

A novel system of nonlinear differential equations is proposed. This system is capable of generating a complex four-wing butterfly chaotic attractor by relying on two embedded state-controlled binary switches. Hence, the system is fully autonomous and does not require external forcing to create this attractor. Furthermore, digital logic operations...

A novel nonautonomous chaotic oscillator based on an active series LC resonator is reported. Excitation is provided by a bipolar pulse-train voltage-source and self feedback via a comparator is employed. The high-dimensional nature of the oscillator is clarified.

It is shown that a recently reported Lorenz-type chaotic system with switching-type nonlinearities can be effectively realised using the switched-capacitor circuit design technique in a simple and straightforward manner. Experimental results from a constructed circuit capable of generating the complex (four-wing) butterfly attractor are shown.

Two new chaotic oscillators with double-scroll dynamics based on the log-domain circuit-design technique are presented. As the circuits operate in log domain, they are suitable for low-voltage, high-frequency operation. The important key parameters of the oscillators are electronically tunable, thus, they are well suited for integrated circuit impl...

A novel high-performance first-order allpass filter with electronically adjustable filter parameters is presented. The core of the circuit is an inverting unity gain amplifier with electronically adjustable output resistance, which leads to an allpass filter realisation with tunable time constant. The circuit is composed of a simple CMOS cascode ci...

We report a novel chaotic oscillator capable of generating n-scroll chaos by relying on multiple-cycle nonlinear transconductor. The function of this nonlinearity can be mathematically represented via smooth hyperbolic tangent functions and its implementation only requires properly-biased bipolar differential-pair cells. A switching square-wave-sha...

It is shown that a new series FDNR-R equivalent circuit using current controlled current conveyors (CCCIIs) allows effective realization of jω-axis zeros which are known to complicate the active implementation of ladder-type elliptic filters. The resulting ladder-type elliptic filter employs all grounded capacitors while keeping the number of activ...

A novel chaotic oscillator capable of generating n-scroll chaos by relying on a multiple-cycle nonlinear transconductor is reported. The function of this nonlinearity can be mathematically represented via smooth hyperbolic tangent functions and its implementation only requires properly-biased bipolar differential-pair cells. The structure of the pr...

An electronic circuit realization of a modified Lorenz system, which is multiplier-free, is described. The well-known butterfly chaotic attractor is experimentally observed verifying that the proposed modified system does capture the essential dynamics of the original Lorenz system. Furthermore, we clarify that the butterfly attractor is a compound...

Bu çalışmada, direnç elemanı içermediğinden tümleştirilmeye uygun, zaman sabiti elektronik olarak kontrol edilebilen iki yeni CMOS birinci derece tümgeçiren süzgeç yapısı önerilmiştir. Sunulan devrelerin basitliği ve büyük giriş işaretleri için de yeterince doğrusal davranmaları en önemli avantajlarıdır. Önerilen tümgeçiren süzgeçlerin SPICE ile ya...