Sebastian A Bota

University of the Balearic Islands | UIB · Department of Physics

This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of a...

Volatile organic compounds (VOCs) have gained the biomedical community attention given their relevance in exhaled human breath analysis for non-invasive disease diagnosis. Today, only bulky, expensive and high-skill bench-top equipment is commercially available to reach the outstanding resolution and selectivity required for their detection. Howeve...

CMOS-MEMS microresonators have become excellent candidates for developing portable chemical VOC sensing systems thanks to their extremely large mass sensitivity, extraordinary miniaturization capabilities, and on-chip integration with CMOS circuitry to operate as a self-sustained oscillator. This paper presents two 4-anchored MEMS plate resonators,...

Physically unclonable functions (PUFs) are used as low-cost cryptographic primitives in device authentication and secret key creation. SRAM-PUFs are well-known as entropy sources; nevertheless, due of non-deterministic noise environment during the power-up process, they are subject to low challenge-response repeatability. The dependability of SRAM-...

In this paper, an schema for controlling the oscillation frequency of a quadrature oscillator is proposed. The method involves controlling the threshold voltage of the PMOS transistors in the inverter through control of the bulk bias voltage. Results obtained using HSPICE simulation are presented in a technology of 0.35{\mu}m, and experimental resu...

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This p...

Physically Unclonable Functions (PUFs) are lowcost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the proces...

SRAM devices are becoming one of the most promising alternatives for the implementation of embedded physical unclonable functions as the start-up value of each bit-cell depends largely on the variability related with the manufacturing process. Not all bit-cells experience the same degree of variability, so it is possible that some cells randomly mo...

Based on experimental data, this paper thoroughly investigates the impact of a gas fluid flow on the behavior of a MEMS resonator specifically oriented to gas sensing. It is demonstrated that the gas stream action itself modifies the device resonance frequency in a way that depends on the resonator clamp shape with a corresponding non-negligible im...

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of...

We present experimental results about the impact of transistor width modulation and power supply voltage variation on the alpha-SER in a 65 nm CMOS 6T SRAM obtained from an accelerated test experiment using an Am-241 alpha source. Five 6T cells with various combinations of transistor widths were tested, results show that nMOS and pMOS widths play a...

The deployment of IoT platforms for SmartCity applications is demanding solutions to assure security and integrity levels. In this context, physical unclonable functions (PUF) may overcome the security drawbacks of storing the security key in a non-volatile memory. The existence of SRAM in embedded systems has driven the implementation of PUF solut...

This paper presents the design, fabrication, and electrical characterization of an electrostatically actuated and capacitive sensed 2-MHz plate resonator structure that exhibits a predicted mass sensitivity of ~250 pg·cm−2·Hz−1. The resonator is embedded in a fully on-chip Pierce oscillator scheme, thus obtaining a quasi-digital output sensor with...

We analyzed experimentally the noise characteristics of fully integrated CMOS-MEMS resonators to determine the overall thermomechanical noise and its impact on the limit of detection at the system level. Measurements from four MEMS resonator geometries designed for ultrasensitive detection operating between 2-MHz and 8-MHz monolithically integrated...

We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliabi...

Microelectromechanical resonators nonlinearities can be exploited in many ways to obtain a set of diverse new applications. In particular, some applications of bistable behavior includes threshold mechanical switches, memory cells, energy harvesting and chaotic signal generators. A key step for practical and efficient design for bistability behavio...

We present experimental results of soft errors produced by proton and neutron irradiation of minimum-size six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories produced with 65 nm CMOS technology using an 18 MeV proton beam and a neutron beam of 4.3–8.5 MeV. All experiments have been carried out at the National Center of Accelerat...

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5–2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, alt...

Technology scaling trends led to an aggressive increase of SRAM cell sensitivity to process variation. More accurate and non-invasive methodologies must be considered to provide detailed bit-cell characterization focusing on writability margin. This work proposes a new metric using regular read/write operations based on the estimation of the maximu...

Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is derived by applying statistical and physics based Montecarlo modeling to the experimental data. Results show that RTN can have a s...

We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write...

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRA...

SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line...

We analyze the evolution of SRAM memory logic contents under irradiation by defining the memory state as the number of cells storing a given logic value (i.e. number of cells storing a logic-1). We find that the memory state evolution under irradiation follows an Ehrenfest urn model due to the constant effect of single event upsets, and that in lar...

Eight-transistor (8T) cells were introduced to improve variability tolerance, cell stability and low-voltage operation in high-speed SRAM caches by decoupling the read and write design requirements. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM. Ionizing radiation effects are nowadays a major concern for reliabil...

The biasing requirements to obtain cross-well chaotic motion for in-plane electrostatically driven beam-shaped MEMS (micro-electromechanical systems) resonators are investigated for typical actuation/readout topologies. Practical applications such as signal chaotic generators require reasonable and wide enough range voltages (dc and ac) to assure a...

In this work we investigate the impact of the in height of FinFET transistors on the Soft Error Rate and Static Noise Margin of a FinFET-based SRAM cell. 3-D TCAD environment is used for the analysis. Results show that increases the fin height of FinFET transistors degrades the radiation robustness of the SRAM cell. However, increases the fin heigh...

We perform a comparative study of the characteristics and capabilities of a pulsed laser system that emulates single event injection available at the UIB with respect to similar pulsed laser test facilities in Europe (EADS, IMS) and the United States (JPL, NRL). A series of experimental measurements were taken on a silicon photodiode (Centronic OSD...

This paper presents experimental results of Soft errors produced by proton interaction in SRAM memories implemented with a 65nm CMOS technology using the 18 MeV proton facility at the National Center of Accelerators (CNA) in Seville.

This paper presents experimental results of Soft errors produced by proton interaction in SRAM memories implemented with a 65nm CMOS technology using the 18 MeV proton facility at the National Center of Accelerators (CNA) in Seville.

We report a detailed analysis about the memory soft error rate (SER) dependence with transistor design parameters for six-transistor (6T) SRAM cells fabricated on a 65-nm CMOS commercial technology. SER data are obtained from accelerated test with an Am-241 alpha source. Five 6T cells with different nMOS and pMOS transistors size combinations were...

Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening. One is related to increasing the number of fins of the transistors composing the cross-coupled inverters. This option provides a significant increas...

Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -the word-line voltage margin (V-WLVM)- and the measured circuit alpha-SER. Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique...

Radiation soft reliability is showing a declining with technology scaling. Because of this new techniques are required to add resilience to the chips. In this work, we analyze the impact of channel width modulation of FinFET SRAM cell transistors by increasing the fin height of FinFET transistor on FinFET SRAM cell hardening. TCAD simulations of th...

We report and analyze the dependence of complex gates delay with the sensitization vector and its variation—that gets up to 40% in 65-nm CMOS technologies—and include its effect in the path delay estimation—that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library pa...

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maint...

Embedded SRAM yield dominates the overall ASIC yield, therefore the methodologies centered on improving SRAM cell stability will be introduced in the design as a mandatory. Word-line voltage modulation has showed that it is possible to improve cell stability during access operations. The high variability of physical and performance parameters intro...

A pulsed laser system has been used to induce single event upsets (SEU) in highly-scaled SRAM devices. The events are induced from the circuit topside in areas where the higher metal layers have been eliminated by design from the circuit layout. The presence of metal tracks for voltage biasing, bit-line and word-line routing, difficult carrying out...

Experimental results from a 65nm CMOS commercial technology SRAM test chip reveal a high correlation between the word-line voltage margin (WVM)-defined as the difference between the memory nominal supply voltage and the lower mean voltage applied to the word-line capable of writing a cell-and the measured circuit alpha-SER. Additional experiments s...

We present a complete EDA tool that quantifies the susceptibility of each node within a combinational circuit to SET propagation. The tool includes a fully analytical SET propagation model developed previously and considers both electrical and logic masking. After an initial path pruning phase based on logical analysis to determine true paths, the...

Radiation sensitivity of SRAM memories is of vital importance in applications demanding high reliability levels. Soft error rates (SER) are usually determined through accelerated tests where target devices are subjected to very high levels of radiation, in order to increase the number of induced events. Two main factors determine the accuracy of th...

Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, advances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and bod...

Resistive bridges are a major class of defects in nanometer technologies that can escape test, posing a serious reliability risk for CMOS IC circuits. The increase of process parameter variations represents a challenge for resistive bridge detection using traditional test methods, and requires more efficient test methods to be developed. In this wo...

The cell static noise margin (SNM) is widely used as a stability criterion for static random-access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable. In this work, we present a methodology that provides an indirect measurement of the SNM on...

We present a Single Event Transient (SET) propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the output noise characteristics given the input noise wave...

We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in...

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) evaluation when in hold mode, although memory errors may also occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SNM of OAM cells during write operations. The W...

We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report and analyze the dependence of complex gates delay with the sensitization vector and its variat...

In this paper we discuss the noise analysis of time variant shapers in the frequency domain, based on well established concepts of the theory of time varying circuits. A frequency domain extension of the techniques typically adopted for noise analysis in detector instrumentation is proposed and applied to a classic time variant shaper: the gated in...

We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about th...

We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65nm CMOS technology show that 6T and 8T cells offer quite similar robustness when they are in hold. However, the critical charge observed in o...

The use of an Electrolyte-SiO 2 -Si system allows a detailed control of the electron injection from the electrolyte into SiO 2 layer, and makes feasible to reach the electron heating in the conduction band of SiO 2 before to take place the irreversible breakdown. The injected and heated electrons enhance the probability of the SiO 2 defect excitati...

A non destructive method to characterize the properties of SiO2 films in SiO2-Si structures and analyze their variations under different external actions is presented and discussed. The method is based on the properties of the Electrolyte-SiO2 contact under polarization which allows us to study the SiO2 film in different injection conditions, in a...

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzi...

A predictive oscillation-based test (POBT) strategy, combined with supply current monitoring, is proposed as an alternative to the specification-based test of analog circuits. According to our simulation results, the combination of both techniques is excellent in predicting the main performance parameters of a CMOS operational amplifier (OpAmp) (dc...

Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common as cell density increases. In this work we propose a Cross-BICS monitoring architecture to enh...

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in tu...

The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer...

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzi...

This paper presents a gamma radiation dosimeter built in a standard 0.35 mum CMOS technology. The dosimeter, which occupies 300 times 150 mum times mum of silicon area, gives a digital output signal of frequency proportional to the total dose. Experimental results up to 1.5 Mrads are presented. Measured low dose radiation responsivity is 84.7 Hz/Kr...

We present the design and operation of a monitor circuit that captures the effect of ionizing particles on sensitive CMOS IC internal nodes. The circuit implements a Single Event Effects (SEE) detector and a quick sampling block that captures the SEE induced waveform shape currents during a certain time window. These values can be read externally t...

In this work we analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor x 1.5 for events produced by alpha particles; this factor is even higher for longer induced current pu...

In this paper, a sequential test technique is proposed to test a RF front-end receiver. With this technique the test circuitry can be reused by the receiver building blocks.The method is suitable to be fully integrated On-Chip. Moreover, the test area overhead has been kept low by using the receiver LO in the test circuitry. Therefore the test circ...

Soft errors resulting from the impact of charged particles are emerging as a major issue in the design of reliable circuits at deep sub-micron dimensions even at ground level. To face this challenge, a designer must dispose of a variety of mitigation schemes adapted to their specific design constraints. Built In Current Sensors have been proposed a...

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all PMOS or al...

In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local osc...

We present an SRAM hardening technique based on combining transistors with different threshold voltages to construct the basic SRAM cell structure. Such a structure maintains the number of transistors and their sizes, while improving the cell robustness. Results show that, for a 90 nm technology, this technique improves Qcrit.

The LHCb experiment is dedicated to precision measurements of CP violation and rare decays of B hadrons at the Large Hadron Collider (LHC) at CERN (Geneva). The initial configuration and expected performance of the detector and associated systems, as established by test beam measurements and simulation studies, is described.

Large detector systems for particle and astroparticle physics; Particle tracking detectors; Gaseous detectors; Calorimeters; Cherenkov detectors; Particle identification methods; Photon detectors for UV. visible and IR photons; Detector alignment and calibration methods; Detector cooling and thermo-stabilization; Detector design and construction te...

This paper presents the circuitry to implement a built-in self test (BiST) strategy for a RF receiver. Using this test strategy fault detection is performed on a LNA. The considered faults are parametrical variations of some LNA elements, and soft opens at selected nodes. After simulations we discuss the detectability margin of these faults. As a r...

The LHCb experiment is dedicated to precision measurements of CP violation and rare decays of B hadrons at the Large Hadron Collider (LHC) at CERN (Geneva). The initial configuration and expected performance of the detector and associated systems, as established by test beam measurements and simulation studies, is described.